TMS4C2972

245760 BY 12-BIT

FIELD MEMORY

SMGS671 – OCTOBER 1997

8

POST OFFICE BOX 1443

reset write (RSTW) (continued)

To clock in a new block address, in case D0 is used, WE and IE must be kept low while this random block address

is clocked in and for at least another 17 SWCK cycles (up through the 34th positive SWCK transition). Otherwise,

if IE is used, WE only must be brought low starting from the 7th up through the 34th SWCK cycle. On the 35th

SWCK cycle, WE and IE may be brought high again. Therefore, earliest possible writing may begin on the 36th

SWCK cycle and proceed sequentially according to the states of control signals WE, IE, and SWCK, as

described in detail in the following sections of the data sheet.

During the previously described sequence, only one positive RSTW transition is allowed. After RSTW has been

kept high during the first positive SWCK transition, it can be maintained high or brought low as desired. But, once

RSTW has gone low, it cannot be brought high again until the end of the entire 36 SWCK cycles sequence.

Bringing RSTW high any earlier may cause improper operation of the device.

For regular device operations, RSTW cannot stay high for more than 1023 SWCK clock cycles while WE is high;

if it does, the device enters a built-in test mode. After RSTW is brought low, it must remain low for at least two

SWCK cycles before another reset write operation can take place.

wrap-around of pointers

It is not necessary to reset the read and write address pointers in case the memory is used as a delay element

only. For this case (that is, if one or both of the pointers are allowed to increment past their maximum values

of 245 771), the following device behavior must be taken into account:

After reaching the value of 245 771, the pointers will wrap around again to value 12. Pointer incrementing will

then be as follows:

0 .... 11

→ 12 ........... 245771 →

→ 12 ........... 245771 →

→ 12 ........... 245771 →

While it is possible to reset one pointer only and let the other pointer wrap around, this is not recommended

because the user would then have to keep track of the location of both write and read information. Such address

tracking is difficult; therefore, it is recommended to either reset both pointers or to let both pointers wrap around.

If the user wishes to terminate wrap-around operation and change over to reset operation again, it is

recommended to proceed as if the entire memory were filled with invalid data, and to write in new data before

attempting the first read-out.

block address

When the block “0000” is addressed by random-block access mode, the pointer is forced to the value 12, that

is, to the same value the pointer assumes after a wrap-around (see previous section). Consequently, the

correspondence between block addresses and pointer values, is as follows:

Block address (hex)

Pointer value (decimal)

0000

12

0001

52

0002

92

....

....

....

....

17FF

245 732

After a FIFO-mode reset-write operation (that is, reset the pointer to address 0), the first 52 words are written

into an internal SRAM cache. On the other hand, if the pointer is set to 12 or block address 0000, the first

40 words are written into the DRAM core. Read access functions in the same manner.