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LPC660 Datasheet(PDF) 8 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part No. LPC660
Description  Low Power CMOS Quad Operational Amplifier
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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 8 page
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Typical Performance Characteristics V
S = ± 7.5V, TA = 25˚C unless otherwise
specified (Continued)
Application Hints
AMPLIFIER TOPOLOGY
The topology chosen for the LPC660 is unconventional
(compared to general-purpose op amps) in that the tradi-
tional unity-gain buffer output stage is not used; instead, the
output is taken directly from the output of the integrator, to al-
low rail-to-rail output swing. Since the buffer traditionally de-
livers the power to the load, while maintaining high op amp
gain and stability, and must withstand shorts to either rail,
these tasks now fall to the integrator.
As a result of these demands, the integrator is a compound
affair with an embedded gain stage that is doubly fed forward
(via C
f and Cff) by a dedicated unity-gain compensation
driver. In addition, the output portion of the integrator is a
push-pull configuration for delivering heavy loads. While
sinking current the whole amplifier path consists of three
gain stages with one stage fed forward, whereas while
sourcing the path contains four gain stages with two fed
forward.
The large signal voltage gain while sourcing is comparable
to traditional bipolar op amps, for load resistance of at least
5k
Ω. The gain while sinking is higher than most CMOS op
Inverting Large-Signal
Pulse Response
DS010547-46
Inverting Small-Signal
Pulse Response
DS010547-47
Stability vs Capacitive Load
DS010547-4
Note: Avoid resistive loads of less than 500
Ω, as they may cause
instability.
Stability vs Capacitive Load
DS010547-5
DS010547-6
FIGURE 1. LPC660 Circuit Topology (Each Amplifier)
www.national.com
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