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FEDL610409-02 Datasheet(PDF) 6 Page - LAPIS Semiconductor Co., Ltd. |
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FEDL610409-02 Datasheet(HTML) 6 Page - LAPIS Semiconductor Co., Ltd. |
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6 / 34 page  FEDL610409-08 ML610407/ML610408/ML610409 6/34 CHIP PAD LAYOUT ML610407 Chip Pad Layout & Dimension Note: The assignment of the pads P30 to P35 are not in order. Chip size: 2.26 mm × 2.17 mm PAD count: 86 pins Minimum PAD pitch: 80 µm PAD aperture: 70 µm×70µm Chip thickness: 350 µm Voltage of the rear side of chip: VSS level. Figure 2 ML610407 Chip Pin Layout & Dimension 28 27 26 25 P53 P54 P55 P56 P57 P35 P33 P32 P34 P31 86 P30 85 P04 84 P03 83 P02 82 P01 81 P00 80 P24 79 P22 78 P21 77 P20 76 VSS SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 COM4/SEG2 COM3/SEG1 COM2/SEG0 COM1 COM0 C2 C1 31 30 29 34 33 32 37 36 35 40 39 38 43 42 41 24 23 22 72 71 70 69 68 67 74 73 Y X 2.17mm 2.26mm 66 75 |
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