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T6818-TUS Datasheet(PDF) 3 Page - ATMEL Corporation |
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T6818-TUS Datasheet(HTML) 3 Page - ATMEL Corporation |
3 / 16 page 3 T6818/T6828 4530C–BCD–11/03 Pin Configuration Figure 2. Pining SO14 GND OUT3 VS CS DI CLK GND GND OUT1 OUT2 VCC INH DO GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Pin Description Pin Symbol Function 1GND T6818: ground; reference potential; internal connection to pin 7, 8 and 14; cooling tab T6828: additional connection to heat slug 2 OUT3 Half-bridge output 3; formed by internally connected power MOS high-side switch 3 and low-side switch 3 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load 3 VS Power supply for output stages OUT1, OUT2 and OUT3, internal supply 4 CS Chip select input; 5-V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled 5 DI Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first 6 CLK Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (f max = 2 MHz) 7 GND Ground; see pin 1 8 GND Ground; see pin 1 9 DO Serial data output; 5-V CMOS logic level tristate output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first); output will remain tristated unless device is selected by CS = low, therefore, several ICs can operate on one data output line only. 10 INH Inhibit input; 5-V logic input with internal pull down; low = standby, high = normal operation 11 VCC Logic supply voltage (5 V) 12 OUT2 Half-bridge output 2; see pin 2 13 OUT1 Half-bridge output 1; see pin 2 14 GND Ground; see pin 1 |
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