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DA14583-01F01AT1 Datasheet(PDF) 11 Page - Dialog Semiconductor |
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DA14583-01F01AT1 Datasheet(HTML) 11 Page - Dialog Semiconductor |
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11 / 150 page  Datasheet Revision 3.0 04-Nov-2016 CFR0011-120-01 11 of 150 © 2014 Dialog Semiconductor DA14583 Bluetooth Low Energy 4.2 SoC with Flash Memory FINAL 4.4 FUNCTIONAL MODES The DA14583 is optimized for deeply embedded appli- cations such as health monitoring, sports measuring, human interaction devices etc. Customers are able to develop and test their own applications. Upon comple- tion of the development, the application code can be programmed into the Flash memory. In general, the system has three functional modes of operation: A. Development Mode: During this phase application code is developed using the ARM Cortex-M0 SW envi- ronment. The compiled code is then downloaded into the System RAM or any Retention RAMs by means of SWD (JTAG) or any serial interface (e.g. UART). Address 0x00 is remapped to the physical memory that contains the code and the CPU is configured to reset and execute code from the remapped device. This mode is enabling application development, debugging and on-the-fly testing. B. Normal Mode: When the application is ready and has been verified, the code can be burned into the embedded Flash memory. When the system boots/ wakes up, the DMA of the OTP controller will automati- cally copy the secondary boot loader from OTP to sys- tem RAM. This boot loader then copies the content of the Flash memory into system RAM. Next, a software reset or a jump to the system RAM occurs and execu- tion of the application code is started. Hence, in this mode the system is autonomous, contains the required software in the Flash memory and is ready for integra- tion into the final product. C. Calibration Mode: Between Development and Nor- mal mode, there is an intermediate stage where the chip needs to be calibrated with respect to two impor- tant features: • Programming of the Bluetooth device address • Programming of the trimming value for the external 16 MHz crystal. This mode of operation applies to the final product and is performed by the customer. During this phase, cer- tain fields in the OTP should be programmed 4.5 POWER MODES The DA14583 supports three different power modes: • Active mode: System is active and operates at full speed. • Sleep mode: No power gating has been pro- grammed, the ARM CPU is idle, waiting for an inter- rupt. PD_SYS is on. PD_PER and PED_RAD depending on the programmed enabled value. • Extended Sleep mode: All power domains are off except for the PD_AON, the programmed PD_RRx and the PD_SR. Since the SysRAM retains its data, no OTP/Flash mirroring is required upon waking up the system. 4.6 INTERFACES 4.6.1 UARTs The UART is compliant to the industry-standard 16550 and is used for serial communication with a peripheral, modem (data carrier equipment, DCE) or data set. Data is written from a master (CPU) over the APB bus to the UART and it is converted to serial form and transmitted to the destination device. Serial data is also received by the UART and stored for the master (CPU) to read back. There is no DMA support on the UART block since its contains internal FIFOs. Both UARTs support hardware flow control signals (RTS, CTS, DTR, DSR). Features • 16 bytes Transmit and receive FIFOs • Hardware flow control support (CTS/RTS) • Shadow registers to reduce software overhead and also include a software programmable reset • Transmitter Holding Register Empty (THRE) inter- rupt mode • IrDA 1.0 SIR mode supporting low power mode. • Functionality based on the 16550 industry standard: • Programmable character properties, such as num- ber of data bits per character (5-8), optional • parity bit (with odd or even select) and number of stop bits (1, 1.5 or 2) • Line break generation and detection • Prioritized interrupt identification • Programmable serial data baud rate as calculated by the following: baud rate = (serial clock frequency)/ (divisor). 4.6.2 SPI+ This interface supports a subset of the Serial Periph- eral Interface SPITM. The serial interface can transmit and receive 8, 16 or 32 bits in master/slave mode and transmit 9 bits in master mode. The SPI + interface has enhanced functionality with bidirectional 2x16-bit word FIFOs. SPI™ is a trademark of Motorola, Inc. Features • Slave and Master mode • 8 bit, 9 bit, 16 bit or 32 bit operation • Clock speeds upto 16 MHz for the SPI controller. Programmable output frequencies of SPI source clock divided by 1, 2, 4, 8 • SPI clock line speed up to 8 MHz • SPI mode 0, 1, 2, 3 support (clock edge and phase) |
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