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TPS2490

TPS2491

SLVS503 – NOVEMBER 2003

DETAILED PIN DESCRIPTION

The following description relies on the typical application diagram shown on page 1, and the functional block

diagram.

VCC:

This pin is associated with three functions: 1) biasing power to the integrated circuit, 2) input to power on

current measurement. The voltage must exceed the POR (about 6 V for roughly 400

µ S) and the internal UVLO

(about 8 V) before normal operation (driving the GATE) may begin. Connections to VCC should be designed to

pin to eliminate transient sensing errors. GATE, PROG, PG, and TIMER are held low when either UVLO or POR

are active.

SENSE:

between SENSE and OUT, while the current analog is the difference between VCC and SENSE. The constant

difference from VCC because it is internally clamped to VCC. The current limit function can be disabled by

connecting SENSE to VCC.

GATE:

Provides the high side (above VCC) gate drive for M1. It is controlled by the internal gate drive amplifier,

which provides a pull-up of 22

µA from an internal charge pump and a strong pull-down to ground of 75 mA

(min). The pull-down current is a non-linear function of the amplifier overdrive; it provides small drive for small

overloads, but large overdrive for fast reaction to an output short. There is a separate pull-down of 2 mA to shut

M1 off when EN or the UVLO cause this to happen. An internal clamp protects the gate of M1 (to OUT) and

(R5) of 10

Ω should be inserted in the gate lead if the C

MOSFETs.

A capacitor can be connected from GATE to ground to create a slower inrush with a constant current profile

without affecting the amplifier stability. Add a series resistor of about 1 k

Ω to the gate capacitor to maintain the

gate clamping and current limit response time.

OUT:

drive OUT below ground, connect a clamp (or freewheel) diode such as an S1B from OUT (cathode) to GND

(anode).

EN:

The GATE driver is enabled if the positive threshold is exceeded and the internal POR and UVLO thresholds

have been satisfied. EN can be used as a logic control input, an analog input voltage monitor as illustrated by

R1/R2 in the typical application circuit on page 1, or it can be tied to VCC to always enable the TPS2490/91. The

hysteresis associated with the internal comparator makes this a stable method of detecting a low input condition

and shutting the downstream circuits off. A TPS2490 that has latched off can be reset by cycling EN below its

negative threshold and back high.

VREF:

Provides a 4.0-V reference voltage for use in conjunction with R3/R4 of the typical application circuit to

set the voltage on the PROG pin. The reference voltage is available once the internal POR and UVLO thresholds

have been met. It is not designed as a supply voltage for other circuitry, therefore ensure that no more than 1 mA

is drawn. Bypass capacitance is not required, but if a special application requires one, less than 1000 pF can be

placed on this pin.

PROG:

The voltage applied to this pin (0–4 V) programs the power limit used by the constant power engine.

Normally, a resistor divider R3/R4 is connected from VREF to PROG to set the power limit according to the

following equation:

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