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TMS320F2801ZGMQ Datasheet(PDF) 8 Page - Texas Instruments |
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TMS320F2801ZGMQ Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 123 page  www.ti.com Revision History TMS320F2808, TMS320F2806 TMS320F2801, UCD9501 Digital Signal Processors SPRS230F – OCTOBER 2003 – REVISED SEPTEMBER 2005 This data manual was revised from SPRS230E to SPRS230F. Substantial additions and changes were made to the electrical specifications section. Scope: this document has been reviewed for technical accuracy; the technical content is up to date as of the specified release date with the following changes: Technical Changes Made for Revision F Location Additions, Deletions, Changes Global: Changed from Advance Information to Production Data. Extensive changes were made to the electrical specifications section, including addition of several new sections. Changed SCIRXB to SCIRXDB and SCITXB to SCITXDB to be consistent with SCIRXDA, etc. Section 1 Added package designators to temperature options on features page Table 2-1 Added information on UCD9501 device nomenclature to Note 2 of the hardware features table and modified other parts of the table Figure 2-1 Modified pinouts for F2808 and F2806, correcting some GPIO options Table 2-2 Modified the descriptions of TRST, XCLKOUT, XCLKIN, X1, ADCREFM, and ADCREFP pins Section 3.2.5 Added information on addresses 0x3F7FF0 - 0x3F7FF5 that are reserved for data variables and changed the note Table 3-1 - Table 3-3 Added a note about programming code security to the three flash sector address tables Section 3.2.16 Changed 12-bit ADC Registers to ADC Result Registers (dual mapped) Table 3-6 Added ADC Result Registers Section 3.4 Modified PartID and RevID information Figure 3-2 Added a reserved address to the F2808 memory map Section 3.2.9 Changed the note about programming code under Code Security Figure 3-3 and Figure 3-4 Modified the Boot ROM address in the memory maps for the F2806, F2801, and UCD9501 devices. Section 3.2.9 Modified description of security and password protection Section 3.2.16 Modified ADC description Table 3-6 Added a row to the Peripheral Frame 0 registers table for ADC Result Registers Table 3-9 Modified Device Emulation Registers table Figure 3-7 Modified the Clock and Reset Domains figure Table 3-13 Modified the descriptions for the XCLK, HISPCP, and LOSPCP registers Figure 3-8 Modified the OSC and PLL Block Diagram Section 3.6.1 Changed the description of the OSC and PLL block Figure 3-11 Split the recommended crystal/clock connection figure into two figures - Using the Internal Oscillator and Using a 3.3-V External Oscillator - and added a third figure, Using a 1.8-V External Oscillator Table 3-14 Modified the PLLCR Register Bit Definitions table Table 3-15 Modified the Possible PLL Configuration Modes table Section 3.6.1.3 Modified description in section on Loss of Input Clock Table 3-16 Modified the Low-Power Modes table Table 4-2 Changed HiRes to HRPWM in the ePWM Control and Status Registers table Figure 4-3 Modified the Multiple PWM Modules in a System table Figure 4-8 Modified ADC Pin Connections With Internal Reference figure Section 4.9 Modified the Serial Peripheral Interface (SPI) features list by deleting the sentence following the baud rate equations Table 4-16 Added F2808 GPIO MUX Table Figure 5-2 Added a figure to show device nomenclature for the UCD family Section 6.1 Changed values in the Absolute Maximum Ratings table and added junction temperature range Section 6.2 Modified the Recommended Operating Conditions table 8 Revision History |
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