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LMX2371SLBX Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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LMX2371SLBX Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 16 page 1.0 Functional Description (Continued) 1.3 PRESCALERS The complimentary f IN and fINB inputs drive a differential-pair amplifier which feeds to the respective prescaler. The Main PLL complementary f IN1 and fIN1b inputs can be driven differentially, or the negative input can be AC coupled to ground through an external capacitor for single ended configuration. The Auxiliary PLL has the complimentary input AC coupled to ground through an internal 10 pF capacitor. The Auxilllary PLL complimentary input is not brought out to a pin, and is intended for single ended configuration only. The LMX237X has a dual modulus prescaler with 2 selectable modulo. For PLL’s rated at 2.5 GHz or 2.0 GHz a 32/33 or 16/17 prescaler is available. For PLL’s rated at 1.2 GHz a 16/17 or 8/9 can be chosen. Both Main and Auxiliary pres- calers’ outputs drive the subsequent CMOS flip-flop chain comprising the programmable N feedback counters. The proper pres- caler value must be chosen to in order not to exceed the maximum CMOS frequency. For f IN > 1.2 GHz, the 32/33 prescaler must be selected, similarly for f IN > 550 MHz, the prescaler value must be at least 16/17, and for fIN < 550 MHz, an 8/9 prescaler value is allowable. 1.4 FEEDBACK DIVIDERS (N-COUNTERS) The Main and Auxiliary N-counters are clocked by the output of Main and Aux prescalers respectively. The N-counter is composed of a 13-bit integer divider and a 5-bit swallow counter. Selecting a 32/33 prescaler provides a minimum continuous divider range from 992 to 262,143 while selecting a 16/17 or 8/9 prescaler value allows for continuous divider values between and 240 to 131,087 and 56 to 65,559 respectively. 1.5 PHASE/FREQUENCY DETECTORS The phase/frequency detectors are driven from their respective N- and R-counter outputs. The maximum frequency at the phase detector inputs is 10 MHz unless limited by the minimum continuous divide ratio of the dual-modulus prescaler. The phase de- tector output controls the charge pump. The polarity of the pump-up or pump-down control is programmed using Main_PD_POL or Aux_PD_POL, depending on whether Main or Auxiliary VCO characteristics is positive or negative. The phase detector also receives a feedback signal from the charge pump in order to eliminate dead zone. 1.6 CHARGE PUMPS The phase detector’s current source output pumps charge into an external loop filter, which then integrates into the VCO’s control voltage. The charge pump steers the charge pump output CP o to VP (pump-up) or Ground (pump-down). When locked, CPo is primarily in a TRI-STATE mode with small corrections. The charge pump output current magnitude can be selected as 1.0 mA or 4.0 mA by programming the Main_ICP o_4X or Aux_ICPo_4X bits. 1.7 MICROWIRE SERIAL INTERFACE The programmable register set is accessed through the Microwire serial interface. The interface is comprised of three signal pins: clock, data and load enable (LE). The supply for the MICROWIRE circuitry is separate from the rest of the IC to allow for controller voltages down to 1.8V. Serial data is clocked into the 22-bit shift register upon the rising edge of clock. The MSB bit of data shifts first. The last two bits decode the internal register address. On the rising edge of LE, data stored in the shift register is loaded into one of the four latches according to the address bits. The synthesizer can be programmed even in power down state. A complete programming description is followed in Section 2.0. 1.8 MULTIFUNCTION OUTPUTS The LMX2370/LMX2371/LMX2372 FoLD output pin can be configured as the FastLock output or CMOS programmed output, analog lock detects as well as showing the internal block status such as the counter outputs. 1.8.1 Lock Detect Output An analog lock detect status generated from the phase detector is available on the Fo/LD output pin, if selected. The lock detect output goes high when the charge pump is inactive. It goes low when the charge pump is active during a comparison cycle. The lock detect signal output is an open drain configuration. When a PLL is in power down mode, the respective lock detect output is always high. 1.8.2 FastLock Outputs When configured as FastLock mode, the current can be increased 4x while maintaining loop stability by synchronously switching a parallel loop filter resistor to ground, resulting in a z2x change in loop bandwidth. The zero gain crossover point of the open loop gain, or the loop bandwidth is effectively shifted up in frequency by a factor of √4 = 2 during FastLock mode. For ω’=2ω, the phase margin during FastLock will also remain constant. The charge pump current is programmed via MICROWIRE interface. When the charge pump circuit receives an input to deliver 4 times the normal current per unit phase error, an open drain NMOS on chip device (FoLD) switches in a second resistor element to ground. The user calculates the loop filter component values for the normal steady state considerations. The device configuration ensures that as long as a second resistor equal to the primary resistor value is wired in appropriately, the loop will lock faster without any additional stability considerations to account for. 1.9 POWER CONTROL Each PLL is individually power controlled by device power-down (PWDN) bits. The Main_PWDN and Aux_PWDN bits determine the state of power control. Activation of any PLL power-down condition results in the disabling of the respective N-counter and de-biasing of its respective f IN input (to a high impedance state). The R-counter functionality also becomes disabled under this condition. www.national.com 6 |
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