[AP1025BEN]

015000434-E-00

- 8 -

2015/01

10.

Functional Description

10.1 Input terminal and protection circuit

 Common description (Parallel input mode and Clock-in input mode)

Table 2. Internal circuit operation by the ENABLE(EN) signal

EN pin

UVLO

TSD

Reference Voltage Circuit

H-Bridge

H

L

L

ON

Output

H

ON

Hi-Z

H

-

OFF

Hi-Z

L

-

-

OFF

Hi-Z

Note 10. UVLO, TSD and Reference Voltage Circuit show internal status. “-“ is Don’t Care.

Table 3. Selection of the chopper frequency by the SYN signal

SYN pin

FS pin

OSC pin

PWM chopper frequency

L

L

Output

25kHz(typ)

H

50kHz(typ)

H

-

Input

External frequency

Note 11. Do not change input level of the SYN and FS pin during operation. “-“ is Don’t Care.

Table 4. Selection of the chopper frequency by the INSEL signal

INSEL

Input Mode

L

Parallel input mode.

H-Bridge is controlled by input logic.

Excitation mode : 2phase, 1-2phase(1/2step), W1-2phase(1/4step)

H

Clock-in input mode.

H-Bridge is controlled by the count number of the clock.

Excitation mode : 2phase, 1-2phase(1/2step), W1-2phase(1/4step), 4W1-2phase(1/16step)

Note 12. Do not change input level of the INSEL terminal during operation.