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AK5556 Datasheet(PDF) 5 Page - Asahi Kasei Microsystems |
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AK5556 Datasheet(HTML) 5 Page - Asahi Kasei Microsystems |
5 / 69 page [AK5556] 015099857-E-00 2016/03 - 5 - ■ Pin Functions No. Pin Name I/O Function Power Down Status 1 AVSS1 - Analog Ground Pin(AIN1-4) - 2 AVDD1 - Analog Power Supply Pin(AIN1-4), 4.5-5.5 V - 3 AIN3P I Channel 3 Positive Input Pin - 4 AIN3N I Channel 3 Negative Input Pin - 5 VREFL2 I ADC Low Level Voltage Reference Input Pin - 6 VREFH2 I ADC High Level Voltage Reference Input Pin - 7 AIN4N I Channel 4 Negative Input Pin - 8 AIN4P I Channel 4 Positive Input Pin - 9 AIN5P I Channel 5 Positive Input Pin - 10 AIN5N I Channel 5 Negative Input Pin - 11 VREFH3 I ADC High Level Voltage Reference Input Pin - 12 VREFL3 I ADC Low Level Voltage Reference Input Pin - 13 AIN6N I Channel 6 Negative Input Pin - 14 AIN6P I Channel 6 Positive Input Pin - 15 AVDD2 - Analog Power Supply Pin(AIN5-6), 4.5-5.5 V - 16 AVSS2 - Analog Ground Pin(AIN5-6) - 17 TESTIN1 I Test Input Pin1 - 18 TESTIN2 I Test Input Pin2 - 19 TESTIN3 I Test Input Pin3 - 20 TESTIN4 I Test Input Pin4 - 21 TESTIN5 I Test Input Pin5 - 22 TESTIN6 I Test Input Pin6 - 23 TEST I TEST Enable Pin. This pin is pull down by 100k Ω internally - 24 MCLK I Master Clock Input Pin - 25 TVDD - Digital I/O Buffers and LDO Power Supply Pin 1.7-1.98 V (LDOE pin= “L”) or 3.0-3.6 V (LDOE pin= “H”). - 26 DVSS - Digital Ground Pin - 27 VDD18 I Digital Core Power Supply Pin, 1.7-1.98 V (LDOE pin= “L”) - O LDO Stabilization Capacitor Connect Pin. (LDOE pin= “H”) Hi-z & Pull Down with 500 Ω 28 PDN I Reset & Power Down Pin “L”: Reset & Power down, “H” : Normal operation - 29 PW0 I Power Management Pin, Channel Summation select Pin - 30 PW1 I Power Management Pin, Channel Summation select Pin - 31 PW2 I Power Management Pin, Channel Summation select Pin - 32 MSN I Master/Slave Select Pin “L”: Slave Mode, “H” : Master Mode - 33 BICK I Audio Serial Data Clock Input Pin in PCM & Slave Mode. This pin is pulled down by 100 k Ω internally - O Audio Serial Data Clock Output Pin in PCM & Master Mode This pin is pulled down by 100 k Ω internally Hi-z DCLK O DSD Clock Output Pin in DSD Mode This pin is pulled down by 100 k Ω internally Hi-z 34 LRCK I Channel Clock Input Pin in PCM & Slave Mode This pin is pulled down by 100 k Ω internally - O Channel Clock Output Pin in PCM & Master Mode This pin is pulled down by 100 k Ω internally Hi-z DSDOL1 O Audio Serial Data Output Pin for AIN1 in DSD Mode This pin is pulled down by 100 k Ω internally Hi-z |
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