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MC68302PV16V Datasheet(PDF) 7 Page - Motorola, Inc |
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MC68302PV16V Datasheet(HTML) 7 Page - Motorola, Inc |
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7 / 480 page  Table of Contents Paragraph Title Page Number Number MOTOROLA MC68302 USER’S MANUAL vii 3.5.3.1 Software Watchdog Timer Operation .................................................... 3-41 3.5.3.2 Software Watchdog Reference Register (WRR) ................................... 3-41 3.5.3.3 Software Watchdog Counter (WCN) ..................................................... 3-42 3.6 External Chip-Select Signals and Wait-State Logic .............................. 3-42 3.6.1 Chip-Select Logic Key Features............................................................ 3-45 3.6.2 Chip-Select Registers............................................................................ 3-45 3.6.2.1 Base Register (BR3–BR0) .................................................................... 3-45 3.6.2.2 Option Registers (OR3–OR0) ............................................................... 3-47 3.6.3 Chip Select Example ............................................................................. 3-48 3.7 On-Chip Clock Generator...................................................................... 3-49 3.8 System Control...................................................................................... 3-50 3.8.1 System Control Register (SCR) ............................................................ 3-50 3.8.2 System Status Bits ................................................................................ 3-51 3.8.3 System Control Bits............................................................................... 3-52 3.8.4 Disable CPU Logic (M68000)................................................................ 3-54 3.8.5 Bus Arbitration Logic ............................................................................. 3-56 3.8.5.1 Internal Bus Arbitration.......................................................................... 3-56 3.8.5.2 External Bus Arbitration......................................................................... 3-58 3.8.6 Hardware Watchdog.............................................................................. 3-59 3.8.7 Reducing Power Consumption.............................................................. 3-60 3.8.7.1 Power-Saving Tips ................................................................................ 3-60 3.8.7.2 Low-Power (Standby) Modes ................................................................ 3-60 3.8.7.2.1 Low-Power Mode .................................................................................. 3-61 3.8.7.2.2 Lowest Power Mode.............................................................................. 3-62 3.8.7.2.3 Lowest Power Mode with External Clock .............................................. 3-62 3.9 Clock Control Register .......................................................................... 3-64 3.9.1 Freeze Control....................................................................................... 3-65 3.10 Dynamic Ram Refresh Controller.......................................................... 3-66 3.10.1 Hardware Setup .................................................................................... 3-66 3.10.2 DRAM Refresh Controller Bus Timing................................................... 3-67 3.10.3 Refresh Request Calculations............................................................... 3-67 3.10.4 Initialization............................................................................................ 3-68 3.10.5 DRAM Refresh Memory Map ................................................................ 3-68 3.10.6 Programming Example.......................................................................... 3-69 Section 4 Communications Processor (CP) 4.1 Main Controller ........................................................................................ 4-1 4.2 SDMA Channels...................................................................................... 4-3 4.3 Command Set ......................................................................................... 4-5 4.3.1 Command Execution Latency ................................................................. 4-7 4.4 Serial Channels Physical Interface.......................................................... 4-7 4.4.1 IDL Interface.......................................................................................... 4-11 4.4.2 GCI Interface ......................................................................................... 4-14 4.4.3 PCM Highway Mode.............................................................................. 4-16 4.4.4 Nonmultiplexed Serial Interface (NMSI) ................................................ 4-19 |
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