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MC68302FC16 Datasheet(PDF) 92 Page - Motorola, Inc |
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MC68302FC16 Datasheet(HTML) 92 Page - Motorola, Inc |
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92 / 480 page  System Integration Block (SIB) 3-42 MC68302 USER’S MANUAL MOTOROLA 3.5.3.3 Software Watchdog Counter (WCN) WCN, a 16-bit up-counter, appears as a memory-mapped register and may be read at any time. Clearing EN in WRR causes the counter to be reset and disables the count operation. A read cycle to WCN causes the current value of the timer to be read. When working in MC68008 mode (BUSW is low), reading the high byte of WCN will latch the low byte into a temporary register. When reading the low byte, the temporary register value is read. Read- ing the timer does not affect the counting operation. A write cycle to WCN causes the counter and prescaler to be reset. In the MC68008 mode (BUSW is low), a write cycle to either the high or low byte resets the counter and the pres- caler. A write cycle should be executed on a regular basis so that the watchdog timer is nev- er allowed to reach the reference value during normal program operation. 3.6 EXTERNAL CHIP-SELECT SIGNALS AND WAIT-STATE LOGIC The MC68302 provides a set of four programmable chip-select signals. Each chip-select signal has an identical internal structure. For each memory area, the user may also define an internally generated cycle termination signal (DTACK). This feature eliminates board space that would be necessary for cycle termination logic. The four chip-select signals allow four different classes of memory to be used: e.g., high- speed static RAM, slower dynamic RAM, EPROM, and nonvolatile RAM. If more than four chip selects are required, additional chip selects may be decoded externally, as on the MC68000. The chip-select block diagram is shown in Figure 3-9. The chip-select logic is active for memory cycles generated by internal bus masters (M68000 core, IDMA, SDMA, DRAM refresh) or external bus masters. These signals are driven externally on the falling edge of AS and are valid shortly after AS goes low. For each chip select, the user programs the block size by choosing the starting address in the base register and the length in the option register. The starting address must be on a block boundary. Thus, an 8K block size must begin on an 8K address boundary, and a 64K block size must begin on a 64K address boundary, etc. For a given chip-select block, the user may also choose 1) whether the chip-select block should be considered as read-only, write-only, or read/write, 2) whether the chip-select block should be active on only one particular function code signal combination or for all func- tion codes, and 3) whether a DTACK should be automatically generated for this chip-select block, and after how many wait states. 15 10 REFERENCE VALUE EN |
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