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LMX1600 Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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LMX1600 Datasheet(HTML) 11 Page - National Semiconductor (TI) |
11 / 14 page 2.0 Programming Description (Continued) 2.5.1 Lock Detect Digital Filter The Lock Detect Digital Filter compares the difference between the phase of the inputs of the phase detector to a RC generated delay of approximately 15 ns. To enter the locked state (Lock = HIGH) the phase error must be less than the 15 ns RC delay for 4 consecutive reference cycles. Once in lock (Lock = HIGH), the RC delay is changed to approximately 30 ns. To exit the locked state (Lock = LOW), the phase error must become greater than the 30 ns RC delay. When the PLL is in the powerdown mode, Lock is forced LOW. A flow chart of the digital filter is shown below. 2.5.2 Typical Lock Detect Timing (AUX_PD_POL/MAIN_PD_POL = 1) DS100129-16 DS100129-17 11 www.national.com |
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