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IDT72V17160 Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT72V17160 Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 26 page  8 INDUSTRIAL TEMPERATURE RANGE IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO AC ELECTRICAL CHARACTERISTICS (Industrial: VCC = 3.3V ± 0.15V, TA = -40 °C to +85°C; JEDEC JESD8-A compliant) NOTES: 1. Pulse widths less than minimum values are not allowed. 2. Values guaranteed by design, not currently tested. Industrial IDT72V15160L10 IDT72V14320L10 IDT72V16160L10 IDT72V15320L10 IDT72V17160L10 IDT72V16320L10 IDT72V18160L10 IDT72V17320L10 IDT72V19160L10 IDT72V18320L10 IDT72V19320L10 Symbol Parameter Min. Max Unit fS Clock Cycle Frequency — 100 Mhz tA Data Access Time 2 6.5 ns tCLK Clock Cycle Time 10 — ns tCLKH Clock High Time 4.5 — ns tCLKL Clock Low Time 4.5 — ns tDS DataSetupTime 3.5 — ns tDH Data Hold Time 0.5 — ns tENS Enable Setup Time 3.5 — ns tENH Enable Hold Time 0.5 — ns tLDS LoadSetupTime 3.5 — ns tLDH Load Hold Time 0.5 — ns tRS Reset Pulse Width(1) 10 — ns tRSS ResetSetupTime 15 — ns tRSR Reset Recovery Time 10 — ns tRSF Reset to Flag and Output Time — 15 ns tOLZ Output Enable to Output in Low Z(2) 0— ns tOE Output Enable to Output Valid 2 6 ns tOHZ Output Enable to Output in High-Z(2) 26 ns tWFF Write Clock to FF — 6.5 ns tREF Read Clock to EF — 6.5 ns tPAFA Clock to Asynchronous Programmable Almost-Full Flag — 16 ns tPAFS Write Clock to Synchronous Programmable Almost-Full Flag — 6.5 ns tPAEA Clock to Asynchronous Programmable Almost-Empty Flag — 16 ns tPAES Read Clock to Synchronous Programmable Almost-Empty Flag — 6.5 ns tHF Clock to HF —16 ns tSKEW1 Skew time between RCLK and WCLK for EF and FF 7— ns tSKEW2 Skew time between RCLK and WCLK for PAE and PAF 10 — ns |
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