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ispGDX160VA-5Q208 Datasheet(PDF) 4 Page - Lattice Semiconductor |
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ispGDX160VA-5Q208 Datasheet(HTML) 4 Page - Lattice Semiconductor |
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4 / 36 page  3 Specifications ispGDX160V/VA Architecture The ispGDXV/VA architecture is different from traditional PLD architectures, in keeping with its unique application focus. The block diagram is shown below. The program- mable interconnect consists of a single Global Routing Pool (GRP). Unlike ispLSI® devices, there are no pro- grammable logic arrays on the device. Control signals for OEs, Clocks/Clock Enables and MUX Controls must come from designated sets of I/O pins. The polarity of these signals can be independently programmed in each I/O cell. Each I/O cell drives a unique pin. The OE control for each I/O pin is independent and may be driven via the GRP by one of the designated I/O pins (I/O-OE set). The I/O-OE set consists of 25% of the total I/O pins. Boundary Scan test is supported by dedicated registers at each I/O pin. In-system programming is accomplished through the standard Boundary Scan protocol. The various I/O pin sets are also shown in the block diagram below. The A, B, C, and D I/O pins are grouped together with one group per side. I/O Architecture Each I/O cell contains a 4:1 dynamic MUX controlled by two select lines as well as a 4x4 crossbar switch con- trolled by software for increased routing flexiability (Figure 1). The four data inputs to the MUX (called M0, M1, M2, and M3) come from I/O signals in the GRP and/or adjacent I/O cells. Each MUX data input can access one quarter of the total I/Os. For example, in a 160 I/O ispGDXV, each data input can connect to one of 40 I/O pins. MUX0 and MUX1 can be driven by designated I/O pins called MUXsel1 and MUXsel2. Each MUXsel input covers 25% of the total I/O pins (e.g. 40 out of 160). MUX0 and MUX1 can be driven from either MUXsel1 or MUXsel2. Figure 1. ispGDXV/VA I/O Cell and GRP Detail (160 I/O Device) I/OCell 0 I/O Cell 1 I/O Cell 78 I/O Cell 79 80 I/O Cells Boundary Scan Cell Bypass Option I/O Cell N Register or Latch I/O Pin Prog. Pull-up (VCCIO) Prog. Slew Rate D A B CLK Reset Q 4-to-1 MUX 160 Input GRP Inputs Vertical Outputs Horizontal I/O Cell 159 I/O Cell 158 I/O Cell 81 M0 I/O Group A I/O Group B I/O Group C I/O Group D M1 4x4 Crossbar Switch M2 M3 MUX1 MUX0 Global Reset I/O Cell 80 • • • • • • • • • 80 I/O Cells ispGDXV/VA architecture enhancements over ispGDX (5V) • • • • • • E2CMOS Programmable Interconnect Logic “0” Logic “1” 160 I/O Inputs C R Y0-Y3 Global Clocks / Clock_Enables Prog. Bus Hold Latch CLK_EN From MUX Outputs of 2 Adjacent I/O Cells From MUX Outputs of 2 Adjacent I/O Cells To 2 Adjacent I/O Cells above To 2 Adjacent I/O Cells below Prog. Open Drain 2.5V/3.3V Output • • • N+1 N+2 N-1 N-2 |
Similar Part No. - ispGDX160VA-5Q208 |
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Similar Description - ispGDX160VA-5Q208 |
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