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ADM6711SAKS Datasheet(PDF) 6 Page - Analog Devices |
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ADM6711SAKS Datasheet(HTML) 6 Page - Analog Devices |
6 / 8 page REV. 0 –6– ADM6711/ADM6713 DETAILED DESCRIPTION The ADM6711/ADM6713 are designed to protect the integrity of a system’s operation by ensuring the proper operation of the system during power-up, power-down, and brownout conditions. When the ADM6711/ADM6713 are powered up, the RESET output will remain low for a period equal to the typical reset active timeout period. This is designed to give the system time to power up correctly and for the power supply to stabilize before any devices are brought out of reset and allowed to begin executing instructions. Initializing a system in this way provides a more reliable startup for microprocessor systems. MANUAL RESET INPUT The ADM6711/ADM6713’s manual reset ( MR) input allows the system operator to reset a system by means of an external manual switch. Alternatively, a logic signal from another digital circuit can be used to trigger a reset via the MR input. The MR input will ignore negative-going pulses faster than 100 ns (typically) and is guaranteed to accept any negative- going input pulse of a duration greater than or equal to 1 µs. The RESET output will remain low while MR is held low and for 240 ms (typically) after MR returns high. If MR is connected to long cables or is used in a noisy environ- ment, then placing a 0.1 µF capacitor between the MR input and ground will help to remove any fast, negative-going transients. POWER SUPPLY GLITCH IMMUNITY The ADM6711/ADM6713 contain internal filtering circuitry that provides immunity to fast transient glitches on the power supply line. TPC 6 illustrates glitch immunity performance by showing the maximum transient duration without causing a reset pulse for glitches with amplitudes in the range of 1 mV to 1000 mV. Glitch immunity makes the ADM6711/ADM6713 suitable for use in noisy environments. Mounting a 0.1 µF decoupling capacitor as close as possible to the VCC pin improves glitch immunity further. ADM6713 RESET OUTPUT LOGIC LEVELS The ADM6713’s open-drain RESET output is designed for use with an external pull-up resistor. This resistor can be tied to VCC or any other reasonable voltage level, offering the flexibility to use the ADM6713 to drive a variety of different logic level circuitry. ENSURING A VALID RESET OUTPUT DOWN TO VCC = 0 V When VCC falls below 0.8 V, the ADM6711’s RESET output no longer sinks current. Therefore, a high impedance CMOS logic input connected to RESET may drift to undetermined logic levels. To eliminate this problem, a pull-down resistor should be connected from RESET to ground. A 100 k Ω resistor is large enough not to load RESET and small enough to pull RESET to ground. VCC VCC GND RESET ADM6711 100k Figure 2. Ensuring a Valid RESET Output Down to VCC = 0 V |
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