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AK5355VN Datasheet(PDF) 8 Page - Asahi Kasei Microsystems |
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AK5355VN Datasheet(HTML) 8 Page - Asahi Kasei Microsystems |
8 / 20 page ASAHI KASEI [AK5355] MS0113-E-01 2005/01 - 8 - SWITCHING CHARACTERISTICS (Ta=25 °C; VA, VD=2.1 ∼ 3.6V; C L=20pF) Parameter Symbol min typ max Units Control Clock Frequency Master Clock (MCLK) 256fs: Frequency Pulse Width Low Pulse Width High 384fs: Frequency Pulse Width Low Pulse Width High 512fs: Frequency Pulse Width Low Pulse Width High Channel Clock (LRCK) Frequency Duty Cycle fCLK tCLKL tCLKH fCLK tCLKL tCLKH fCLK tCLKL tCLKH fs duty 2.048 28 28 3.072 23 23 4.096 16 16 8 45 11.2896 16.9344 22.5792 44.1 12.8 19.2 25.6 50 55 MHz ns ns MHz ns ns MHz ns ns kHz % Audio Interface Timing BCLK Period BCLK Pulse Width Low Pulse Width High BCLK “ ↓” to LRCK LRCK Edge to SDTO (MSB) BCLK “ ↓” to SDTO tBLK tBLKL tBLKH tBLR tDLR tDSS 312.5 130 130 -tBLKH+50 tBLKL-50 80 80 ns ns ns ns ns ns Reset / Initializing Timing PDN Pulse Width PDN “ ↑” to SDTO (Note 8) tPW tPWV 150 4128 ns 1/fs Note 8. This is the number of LRCK rising after the PDN pin is pulled high. |
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