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LMF100CIWM Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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LMF100CIWM Datasheet(HTML) 8 Page - National Semiconductor (TI) |
8 / 28 page Pin Descriptions LP(1,20), BP(2,19), N/AP/HP(3,18) The second order lowpass, bandpass and notch/allpass/highpass outputs. These outputs can typically swing to within 1V of each supply when drivinga5k Ω load. For optimum performance, capacitive loading on these outputs should be minimized. For signal frequencies above 15 kHz the capacitance loading should be kept below 30 pF. INV(4,17) The inverting input of the summing opamp of each filter. These are high impedance inputs. The non-inverting input is internally tied to AGND so the opamp can be used only as an inverting amplifier. S1(5,16) S1 is a signal input pin used in modes 1b, 4, and 5. The input impedance is 1/f CLK x 1 pF. The pin should be driven with a source impedance of less than 1 k Ω.If S1 is not driven with a signal it should be tied to AGND (mid-supply). S A/B(6) This pin activates a switch that connects one of the inputs of each filter’s second summer either to AGND (S A/B tied to V −)ortothe lowpass (LP) output (S A/B tied to V +). This offers the flexibility needed for configuring the filter in its various modes of operation. V A +(7) (Note 15) This is both the analog and digital positive supply. V D +(8) (Note 15) This pin needs to be tied to V + except when the device is to operate on a single 5V supply and a TTL level clock is applied. For 5V, TTL operation, V D + should be tied to ground (0V). V A −(14), V D −(13) Analog and digital negative supplies. V A −and V D − should be derived from the same source. They have been brought out separately so they can be bypassed by separate capacitors, if desired. They can also be tied together externally and bypassed with a single capacitor. LSh(9) Level shift pin. This is used to accommodate various clock levels with dual or single supply operation. With dual ±5V supplies and CMOS (±5V) or TTL (0V–5V) clock levels, LSh should be tied to system ground. For 0V–10V single supply operation the AGND pin should be biased at +5V and the LSh pin should be tied to the system ground for TTL clock levels. LSh should be biased at +5V for ±5V CMOS clock levels. The LSh pin is tied to system ground for ±2.5V operation. For single 5V operation the LSh and V D+ pins are tied to system ground for TTL clock levels. CLK(10,11) Clock inputs for the two switched capacitor filter sections. Unipolar or bipolar clock levels may be applied to the CLK inputs according to the programming voltage applied to the LSh pin. The duty cycle of the clock should be close to 50%, especially when clock frequencies above 200 kHz are used. This allows the maximum time for the internal opamps to settle, which yields optimum filter performance. 50/100(12) (Note 15) By tying this pin to V + a 50:1 clock to filter center frequency ratio is obtained. Tying this pin at mid-supply (i.e., system ground with dual supplies) or to V − allows the filter to operate at a 100:1 clock to center frequency ratio. AGND(15) This is the analog ground pin. This pin should be connected to the system ground for dual supply operation or biased to mid-supply for single supply operation. For a further discussion of mid-supply biasing techniques see the Applications Information (Section 3.2). For optimum filter performance a “clean” ground must be provided. Note 15: This device is pin-for-pin compatible with the MF10 except for the following changes: 1. Unlike the MF10, the LMF100 has a single positive supply pin (VA+). 2. On the LMF100 VD + is a control pin and is not the digital positive supply as on the MF10. 3. Unlike the MF10, the LMF100 does not support the current limiting mode. When the 50/100 pin is tied to V− the LMF100 will remain in the 100:1 mode. www.national.com 8 |
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