SiC401, SiC402, SiC403

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Vishay Siliconix

Revision: 17-Nov-14

5

Document Number: 62923

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

LAYOUT CONSIDERATIONS

The SiC40x family of footprint compatible 15 A, 10 A, and

6 A products offers the designer a scalable buck regulator

solution. If the below layout recommendations are followed,

the same layout can be used to cover a wide range of output

currents and voltages without any changes to the board

design and only minor changes to the component values in

the schematic.

The reference design has a majority of the components

placed on the top layer. This allows for easy assembly and

straightforward layout.

Figure 2 outlines the pointers for the layout considerations

and the explanations follow.

1. Place input ceramic capacitors close to the voltage input

pins with a small 10 nF / 100 nF placed as close as the

design rules will allow. This will help reduce the size of

the input high frequency current loop and consequently

reduce the high frequency ripple noise seen at the input

and the LX node.

2. Place the setup and control passive devices logically

around the IC with the intention of placing a quiet ground

plane beneath them on a secondary layer.

3. It is advisable to use ceramic capacitors at the output to

and output voltage node as design will allow. Place a

small 10 nF / 100 nF ceramic capacitor closest to the IC

and inductor loop.

compact as possible. This will lower series resistance

and also make the current loop smaller enabling the high

frequency response of the output capacitors to take

effect.

5. The output impedance should be small when high

current is required; use high current traces, multiple

layers can be used with many vias.

6. Use many vias when multiple layers are involved. This

will have the effect of lowering the resistance between

layers and reducing the via inductance of the PCB nets.

7. If a voltage injection network is needed then place it near

to the inductor LX node.

the PCB is to be small; this will also help remove heat.

Use extra vias if needed but be mindful to allow a path

between the vias.

placed under the small signal passives. This can be

placed on multiple layers if needed for heat removal. This

GND at one connection only of at least 1mm width.

10. The LX copper can also be used on multiple layers, use

a number of vias.

11. The copper area beneath the inductor has been removed

(on all layers) in this design to reduce the inductive

coupling that occurs between the inductor and the GND

trace. No other voltage planes should be placed under

this area.