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ISOW7842FDWE Datasheet(PDF) 11 Page - Texas Instruments |
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ISOW7842FDWE Datasheet(HTML) 11 Page - Texas Instruments |
11 / 38 page 11 ISOW7840, ISOW7841, ISOW7842, ISOW7843, ISOW7844 www.ti.com SLLSEY2 – MARCH 2017 Product Folder Links: ISOW7840 ISOW7841 ISOW7842 ISOW7843 ISOW7844 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) VSI= input side supply; VSO= output side supply (2) Current available to load should be derated by 2 mA/°C for TA > 115°C. 7.11 DC Electrical Characteristics—3.3-V Input, 3.3-V Output These specifications are for the ISOW7841 and ISOW7841F devices only; VCC = 3.3 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ICC Current drawn from supply No external IISO; VI = 0 V (ISOW7841); VI = VS (1) (ISOW7841 with F suffix) 26 mA No external IISO; VI = VSI (ISOW7841); VI = 0 V (ISOW7841 with F suffix) 20 All channels switching with square wave clock input of 0.5 MHz; CL = 15 pF, No external IISO 23 All channels switching with square wave clock input of 5 MHz; CL = 15 pF, No external IISO 26 All channels switching with square wave clock input of 50 MHz; CL = 15 pF, No external IISO 53 IISO(OUT) (2) Current available to isolated supply VI = 0 V (ISOW7841); VI = VSI (ISOW7841 with F suffix) 73 mA VI = VSI(ISOW7841); VI = 0 V (ISOW7841 with F suffix) 75 All channels switching with square wave clock input of 0.5 MHz; CL= 15 pF 74 All channels switching with square wave clock input of 5 MHz; CL = 15 pF 73 All channels switching with square wave clock input of 50 MHz; CL = 15 pF 61 VISO Isolated supply voltage External IISO = 0 to 30 mA 3.13 3.34 3.58 V External IISO = 0 to 75 mA 3 3.34 3.58 VISO(LINE) DC line regulation IISO = 30 mA, VCC = 3 V to 3.6 V 2 mV/V VISO(LOAD) DC load regulation IISO = 0 to 75 mA 1% EFF Efficiency at maximum load current IISO = 75 mA, CLOAD = 0.1 µF || 10 µF; VI = VSI (ISOW7841); VI = 0 V (ISOW7841 with F suffix) 47% VCC+(UVLO) Positive-going UVLO threshold on VCC, VISO 2.7 V VCC–(UVLO) Negative-going UVLO threshold on VCC, VISO 2.1 V VHYS (UVLO) UVLO threshold hysteresis on VCC, VISO 0.2 V VITH Input pin rising threshold 0.7 VSI VITL Input pin falling threshold 0.3 VSI VI(HYS) Input pin threshold hysteresis (INx) 0.1 VSI IIL Low level input current VIL = 0 at INx or SEL –10 µA IIH High level input current VIH = VSI (1) at INx or SEL 10 µA VOH High level output voltage IO = –2 mA, see Figure 24 VSO (1) – 0.3 VSO – 0.1 V VOL Low level output voltage IO = 2 mA, see Figure 24 0.1 0.3 V CMTI Common mode transient immunity VI = VSI or 0 V, VCM = 1000 V; see Figure 25 100 kV/us ICC_SC DC current from supply under short circuit on VISO VISO shorted to GND2 143 mA VISO(RIP) Output ripple on isolated supply (pk-pk) 20-MHz bandwidth, CLOAD = 0.1 µF || 20 µF, IISO = 75 mA 90 mV |
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