THCV226_Rev.1.10_E

Copyright©2015 THine Electronics, Inc.

THine Electronics, Inc.

Security E

LVDS Output Enable Function

By setting the OE and OPF pins, the following output enable function can be selected.

In output disable condition, all the outputs take low fixed data or High-Z except for HTPDN, LOCKN and

DGLOCK.

LOCKN

OE

OPF

LVDS Outputs

Status

Output Condition

H

1

1

Output Enable

Low Fixed Data

0

Hi-Z

0

1

Output Disable

Low Fixed Data

0

Hi-Z

L

1

1

Output Enable

Normal Data

0

0

1

Output Disable

Low Fixed Data

0

Hi-Z

Table 7. LVDS Output Enable Function

LVDS Data Mapping

LVDS data (video data, control data, DE) are mapped as Figure 9. RLC[6] is special bit for DE (data enable).

RLC[5:4] are for control data bits, and the other bits are for video data. Also there are special assigned bits,

‘CTL’ transmitted under DE=0 condition.

The number of LVDS channels depends on color depth mode, COL.

RLD[6] is not available at COL=0, 8-bit color depth mode.

Vdiff = 0

RLAzp/n

(RLCLKzp) – (RLCLKzn)

Figure 9. LVDS Output Switching Timing Diagram

RLBzp/n

RLCzp/n

RLDzp/n

RLEzp/n

RLAz[0]

tRCOP

Previous cycle

Current cycle

Next cycle

z = 0,1,2,3

RLAz[1]

RLAz[2]

RLAz[3]

RLAz[4]

RLAz[5]

RLAz[6]

RLAz[0]

RLAz[1]

RLAz[2]

RLAz[3]

RLAz[4]

RLAz[5]

RLAz[6]

RLAz[0]

RLAz[1]

RLBz[0]

RLBz[1]

RLBz[2]

RLBz[3]

RLBz[4]

RLBz[5]

RLBz[6]

RLBz[0]

RLBz[1]

RLBz[2]

RLBz[3]

RLBz[4]

RLBz[5]

RLBz[6]

RLBz[0]

RLBz[1]

RLCz[0]

RLCz[1]

RLCz[2]

RLCz[3]

RLCz[4]

(H)

RLCz[5]

(V)

RLCz[6]

(DE)

RLCz[0]

RLCz[1]

RLCz[2]

RLCz[3]

RLCz[4]

(H)

RLCz[5]

(V)

RLCz[6]

(DE)

RLCz[0]

RLCz[1]

RLDz[0]

RLDz[1]

RLDz[2]

RLDz[3]

RLDz[4]

RLDz[5]

RLDz[6]

RLDz[0]

RLDz[1]

RLDz[2]

RLDz[3]

RLDz[4]

RLDz[5]

RLDz[6]

RLDz[0]

RLDz[1]

RLEz[0]

RLEz[1]

RLEz[2]

RLEz[3]

RLEz[4]

RLEz[5]

RLEz[6]

RLEz[0]

RLEz[1]

RLEz[2]

RLEz[3]

RLEz[4]

RLEz[5]

RLEz[6]

RLEz[0]

RLEz[1]

Data Enable

Control Data Bits

Data width

32 24

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