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MAX1479ATE Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX1479ATE Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 11 page 300MHz to 450MHz Low-Power, Crystal-Based +10dBm ASK/FSK Transmitter 6 _______________________________________________________________________________________ Detailed Description The MAX1479 is a highly integrated ASK/FSK transmit- ter operating over the 300MHz to 450MHz frequency band. The device requires only a few external compo- nents to complete a transmitter solution. The MAX1479 includes a complete PLL and a highly efficient power amplifier. The device can be set into a 0.2nA low-power shutdown mode. Shutdown Mode ENABLE (pin 4) is internally pulled down with a 20µA current source. If it is left unconnected or pulled low, the MAX1479 goes into a low-power shutdown mode. In this mode, the supply current drops to 0.2nA. When ENABLE is high, the device is enabled and is ready for transmission after 200µs (frequency settles to within 50kHz). The 200µs turn-on time of the MAX1479 is mostly domi- nated by the crystal oscillator startup time. Once the oscillator is running, the 300kHz PLL bandwidth allows fast frequency recovery during power-amplifier toggling. Mode Selection MODE (pin 2) sets the MAX1479 in either ASK or FSK mode. When MODE is set low, the device operates as an ASK transmitter. If MODE is set high, the device operates as an FSK transmitter. In the ASK mode, the DIN pin controls the output of the power amplifier. A logic low on DIN turns off the PA, and a logic high turns on the PA. In the FSK mode, a logic low on the DIN pin is represented by the low FSK frequency, and a logic- high input is represented by the high FSK frequency. (The ASK carrier frequency and the lower FSK frequen- cy are the same.) The deviation is proportional to the crystal load impedance and pulling capacitance. The maximum frequency deviation is 55kHz for fRF = 315MHz and 80kHz for fRF = 433MHz. Pin Description PIN NAME DESCRIPTION 1VDD Supply Voltage. Bypass to GND with a 10nF and 220pF capacitor as close to the pin as possible. 2 MODE Mode Select. A logic low on MODE enables the device in ASK mode. A logic high on MODE enables the device in FSK mode. 3DIN Data Input. Power amplifier is on when DIN is high in ASK mode. Frequency is high when DIN is high in FSK mode. 4 ENABLE Standby/Power-Up Input. A logic low on ENABLE sets the device in standby mode. 5 CLKOUT Buffered Clock Output. Programmable through CLK0 and CLK1. See Table 1. 6 VDD_PA Power-Amplifier Supply Voltage. Bypass to GND with a 10nF and 220pF capacitor as close to the pin as possible. 7ROUT Envelope-Shaping Output. ROUT controls the power-amplifier envelope rise and fall. Bypass to GND with a 680pF and 220pF capacitor as close to the pin as possible. 8 PAOUT Power-Amplifier Output. Requires a pullup inductor to the supply voltage, which can be part of the output- matching network to an antenna. 9 CLK0 1st Clock Divider Setting. See Table 1. 10 CLK1 2nd Clock Divider Setting. See Table 1. 11 DEV0 1st FSK Frequency-Deviation Setting. See Table 2. 12 DEV1 2nd FSK Frequency-Deviation Setting. See Table 2. 13 DEV2 3rd FSK Frequency-Deviation Setting. See Table 2. 14 XTAL1 1st Crystal Input. fRF = 32 x fXTAL. 15 XTAL2 2nd Crystal Input. fRF = 32 x fXTAL. 16 GND Ground. Connect to system ground. —EP Exposed Ground Paddle. EP is the power amplifier’s ground. It must be connected to PC board through a low-inductance path. |
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