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DRV3220QPHPRQ1 Datasheet(PDF) 9 Page - Texas Instruments

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Part # DRV3220QPHPRQ1
Description  Three-Phase Automotive Gate Driver With Enhanced Protection, Diagnostics, and Monitoring
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DRV3220QPHPRQ1 Datasheet(HTML) 9 Page - Texas Instruments

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9
DRV3220-Q1
www.ti.com
SLVSDM3 – FEBRUARY 2017
Product Folder Links: DRV3220-Q1
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Copyright © 2017, Texas Instruments Incorporated
Electrical Characteristics (continued)
over operating temperature TJ = –40°C to 150°C and recommended operating conditions, VS = 4.75 V to 40 V
(1), ƒ
PWM < 20
kHz (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(4)
During startup when BOOST – VS < VBOOSTUV , ƒBOOST is typically 1.25 MHz.
(5)
All digital outputs have a push-pull output stage between VDDIO and ground.
6.
BOOST CONVERTER
6.1
VBOOST
Boost output voltage excluding
switching ripple and response
delay.
BOOST – VS voltage
14
15
16.5
V
6.1b
VBOOSTOV
Boost output voltage overvoltage
with respect GND
64
67.5
70
V
6.2
IBOOST
Output current capability
External load current including external
MOSFET gate charge current
BOOST – VS > VBOOSTUV
40
mA
6.3
ƒBOOST
Switching frequency
BOOST – VS > VBOOSTUV; ensured by
characterization(4)
1.8
2.5
3
MHz
6.31
BOOST – VS > VBOOSTUV; VS < 6 V; ensured
by characterization (4)
1.1
3
6.4
VBOOSTUV
Undervoltage shutdown level
BOOST – VS voltage
7
8
V
6.4a
VBOOSTUV2
Undervoltage condition that
device may enter RESET state
BOOST – GND voltage
10
V
6.5
tBCSD
Filter time for undervoltage
detection
5
6
µs
6.7
VGNDLS_B,off
Voltage at GNDLS_B pin at
which boost FET switches off
because of current limit
110
150
200
mV
6.7a
tSW,off
Delay of the GNDLS_B current
limit comparator
Specified by design
100
ns
6.8
ISW,fail
Internal second-level current limit
GNDLS_B = 0 V
840
1600
mA
6.9
Rdson_BSTfet
Rdson resistance boost FET
VS ≥ 6; ISW = VGNDLS_B,off / 0.33 Ω
0.25
1.5
Ω
6.9a
VS < 6; ISW= VGNDLS_B,off / 0.33 Ω
2
Ω
7.
DIGITAL INPUTS
7.1
INL
Input low threshold
All digital inputs NCS, DRVOFF, ILSx, IHSx,
SDI
VDDIO × 0.3
V
7.1a
ENH
EN input high threshold
VS > 4 V
2.7
V
7.1b
ENL
EN input low threshold
VS > 4 V
0.7
V
7.2
INH
Input high threshold
All digital inputs NCS, DRVOFF, ILSx, IHSx,
SDI
VDDIO × 0.7
V
7.3
Inhys
Input hysteresis
All digital inputs EN, NCS, DRVOFF, ILSx,
IHSx, SDI, VDDIO = 5 V
0.3
0.4
V
7.3a
All digital inputs EN, NCS, DRVOFF, ILSx,
IHSx, SDI, VDDIO = 3.3 V
0.2
0.3
V
7.4
Rpd,EN
Input pulldown resistor at EN pin
EN
140
200
360
7.4a
tdeg,ENon
Power-up time after EN pin high
from sleep mode to active mode
ERR = L
→ H
5
ms
7.5
Rpullup
Input pullup resistance
NCS, DRVOFF
200
280
400
7.6
Rpulldown
Input pulldown resistance
ILSx, IHSx, SDI , SCLK Input voltage = 0.1 V
100
140
200
7.6a
Rpulldown
Input pulldown current
ILSx, IHSx, SDI, SCLK Input voltage =
VDDIO
4
50
µA
8.
DIGITAL OUTPUTS
8.1
OH1
Output high voltage 1
All digital outputs: SDO, I = ±2 mA; VDDIO in
functional range(5)
VDDIO × 0.9
V
8.2
OL1
Output low voltage 1
All digital outputs: SDO, I = ±2 mA; VDDIO in
functional range
VDDIO × 0.1
V
8.1
OH2
Output high voltage 2
ERR I = –0.2 mA; VDDIO in functional range
VDDIO × 0.9
V
8.2
OL2
Output low voltage 2
ERR I = +0.2 mA; VDDIO in functional range
VDDIO × 0.1
V
9.
VDS, VGS, MONITORING
9.1
VSCTH
VDS short-circuit threshold range If not disabled in CFG1
0.1
2
V


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