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MB90F543PFV Datasheet(PDF) 5 Page - Fujitsu Component Limited. |
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MB90F543PFV Datasheet(HTML) 5 Page - Fujitsu Component Limited. |
5 / 67 page MB90540/540G/545/545G Series 5 (Continued) *1 : Under development *2 : If the one clock system is used, equip X0A and X1A with clocks from the tool side. Features MB90F543/F549 MB90F543G (S) /F548G (S) MB90F549G (S) /F546G (S) MB90F548GL(S) MB90543G (S) *1 MB90547G (S) *1 MB90548G (S) MB90549G (S) MB90V540 MB90V540G 16-bit Reload Timer (2 channels) Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function Signals an interrupt when overflow 16-bit I/O Timer Supports Timer Clear when a match with Output Compare (Channel 0) Operation clock freq. : fsys/22, fsys/24, fsys/26, fsys/28 (fsys = System clock freq.) 16-bit Output Compare (4 channels) Signals an interrupt when a match with 16-bit I/O Timer Four 16-bit compare registers A pair of compare registers can be used to generate an output signal 16-bit Input Capture (8 channels) Rising edge, falling edge or rising & falling edge sensitive Four 16-bit Capture registers Signals an interrupt upon external event 8/16-bit Programmable Pulse Generator (4 channels) Supports 8-bit and 16-bit operation modes Eight 8-bit reload counters Eight 8-bit reload registers for L pulse width Eight 8-bit reload registers for H pulse width A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter 4 output pins Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz (fsys = System clock frequency, fosc = Oscillation clock frequency) CAN Interface MB90540 series : 2 channels MB90545 series : 1 channel Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 massage buffers for data and ID’s supports multipe massages Flexible configuration of acceptance filtering : Full bit compare/Full bit mask/Two partial bit masks Supports up to 1 Mbps 32 kHz Sub-clock Sub-clock for low power operation External Interrupt (8 channels) Can be programmed edge sensitive or level sensitive External bus interface External access using the selectable 8-bit or 16-bit bus is enabled (external bus mode.) I/O Ports Virtually all external pins can be used as general purpose I/O All push-pull outputs and schmitt trigger inputs Bit-wise programmable as input/output or peripheral signal Sub-clock for 32 kHz Sub clock low power operation Flash Memory Supports automatic programming, Embeded Algorithm TM*4 Write/Erase/Erase-Suspend/Erase-Resume commands A flag indicating completion of the algorithm Number of erase cycles : 10,000 times Data retention time : 10 years Boot block configuration Erase can be performed on each block Block protection by externally programmed voltage |
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Similar Description - MB90F543PFV |
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