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MC56F8323VFB60 Datasheet(PDF) 3 Page - Motorola, Inc |
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MC56F8323VFB60 Datasheet(HTML) 3 Page - Motorola, Inc |
3 / 140 page 56F8323 Technical Data, Rev. 11.0 Freescale Semiconductor 3 Preliminary 56F8323/56F8123 Block Diagram Program Controller and Hardware Looping Unit Data ALU 16 x 16 + 36 −> 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Address Generation Unit Bit Manipulation Unit 16-Bit 56800E Core Interrupt Controller COP/ Watchdog 4 IRQA PDB PDB XAB1 XAB2 XDB2 CDBR SPI0 or SCI1 or GPIOB IPBus Bridge (IPBB) Decoding Peripherals Peripheral Device Selects RW Control IPAB IPWDB IPRDB System Bus Control R/W Control PAB PAB CDBW CDBR CDBW JTAG/ EOnCE Port Digital Reg Analog Reg Low Voltage Supervisor VDD VSS VDDA VSSA 5 44 2 RESET 3 6 Quad Timer C or SCI0 or GPIOC 5 Quadrature Decoder 0 or Quad Timer A or GPIO B FlexCAN or GPIOC 2 4 VREF PLL Clock Generator* Integration Module System P O R O S C Clock resets PWM Outputs Current Sense Inputs PWMA or SPI1 or GPIOA TEMP_SENSE *Includes On-Chip Relaxation Oscillator 3 Fault Inputs OCR_DIS VCAP 4 3 AD0 4 AD1 4 XTAL or GPIOC EXTAL or GPIOC Data Memory 4K x 16 Flash 4K x 16 RAM Memory Program Memory 16K x 16 Flash 2K x 16 RAM 4K x 16 Boot Flash 56F8323/56F8123 General Description Note: Features in italics are NOT available in the 56F8123 device. • Up to 60 MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • 32KB Program Flash • 4KB Program RAM • 8KB Data Flash • 8KB Data RAM •8KB Boot Flash • One 6-channel PWM module • Two 4-channel 12-bit ADCs • Temperature Sensor • One Quadrature Decoder • One FlexCAN module • Up to two Serial Communication Interfaces (SCIs) • Up to two Serial Peripheral Interfaces (SPIs) • Two general-purpose Quad Timers • Computer Operating Properly (COP)/Watchdog • On-Chip Relaxation Oscillator • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging •Up to 27 GPIO lines • 64-pin LQFP Package |
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Similar Description - MC56F8323VFB60 |
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