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ZSSC3015NA1B Datasheet(PDF) 4 Page - Integrated Device Technology

Part # ZSSC3015NA1B
Description  Sensor Signal Conditioner with Diagnostics
Download  48 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ZSSC3015NA1B Datasheet(HTML) 4 Page - Integrated Device Technology

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ZSSC3015 Datasheet
© 2016 Integrated Device Technology, Inc.
4
January 20, 2016
3.7.
Calibration Math ...................................................................................................................................... 34
3.7.1.
Correction Coefficients...................................................................................................................... 34
3.7.2.
Interpretation of Binary Numbers for Correction Coefficients ........................................................... 35
3.8.
Reading EEPROM Contents ................................................................................................................... 38
4
Application Circuit Examples.......................................................................................................................... 39
4.1.
Three-Wire Rail-to-Rail Ratiometric Output............................................................................................. 39
4.2.
Absolute Analog Voltage Output ............................................................................................................. 40
4.3.
Three-Wire Ratiometric Output with Over-Voltage Protection ................................................................ 41
4.4.
Digital Output ........................................................................................................................................... 41
4.5.
Output Resistor/Capacitor Limits............................................................................................................. 41
5
EEPROM Restoration .................................................................................................................................... 42
5.1.
Default EEPROM Contents ..................................................................................................................... 42
5.1.1.
1V_Trim/JFET_Trim.......................................................................................................................... 42
5.2.
EEPROM Restoration Procedure ............................................................................................................ 42
6
Pin Configuration and Package...................................................................................................................... 44
7
ESD/Latch-Up-Protection ............................................................................................................................... 45
8
Test................................................................................................................................................................. 45
9
Quality and Reliability..................................................................................................................................... 45
10 Customization................................................................................................................................................. 45
11 Ordering Sales Codes .................................................................................................................................... 46
12 Related Documents........................................................................................................................................ 46
13 Definitions of Acronyms.................................................................................................................................. 47
14 Document Revision History ............................................................................................................................ 48
List of Figures
Figure 2.1
ZSSC3015 Block Diagram ................................................................................................................ 11
Figure 2.2
DAC Output Timing for Highest Update Rate................................................................................... 15
Figure 3.1
General Working Mode ..................................................................................................................... 21
Figure 3.2
Manchester Duty Cycle..................................................................................................................... 23
Figure 3.3
19-Bit Write Frame............................................................................................................................ 24
Figure 3.4
Read Acknowledge ........................................................................................................................... 24
Figure 3.5
Digital Output (NOM) Bridge Readings ............................................................................................ 25
Figure 3.6
Digital Output (NOM) Bridge Readings with Temperature ............................................................... 25
Figure 3.7
Read EEPROM Contents ................................................................................................................. 26
Figure 3.8
Transmission of a Number of Data Packets ..................................................................................... 26
Figure 3.9
ZACwire™ Output Timing for Lower Update Rates.......................................................................... 27
Figure 4.1
Rail-to-Rail Ratiometric Voltage Output – Temperature Compensation via External Diode ............ 39
Figure 4.2
Absolute Analog Voltage Output – Temperature Compensation via External Diode with External
JFET Regulation ............................................................................................................................... 40
Figure 4.3
Ratiometric Output, Temperature Compensation via Internal PTAT................................................ 41
Figure 5.1
EEPROM Validation and Restoration Procedure ............................................................................. 43


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