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ZSSC3036CI1C Datasheet(PDF) 8 Page - Integrated Device Technology |
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ZSSC3036CI1C Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 48 page  ZSSC3036 Datasheet © 2016 Integrated Device Technology, Inc. 8 April 20, 2016 Parameter Symbol Conditions/Comments Min Typ Max Unit Analog-to-Digital Converter (ADC, A2D) Resolution rADC 10 16 Bit ADC Clock Frequency fADC Internal ADC clock 1.3 1.5 1.7 MHz Reference Voltage n Vrefn VDDB * 0.03 Reference Voltage p Vrefp VDDB * 0.97 Offset A2D_Offset 8-step programmable offset 1/16 8/16 Integral Nonlinearity (INL) INLADC Based on ideal slope -4 - +4 LSB Differential Nonlinearity DNLADC Tested / verified within design -1 - +1 LSB Conversion Rate, 16-Bit Single fS,raw Conversions per second for single 16-bit A2D conversion 15 - 1015 Hz Amplifier Gain Gamp 32 steps 13.2 72 Gain Error Gerr Referenced to nominal gain -1.5 - 1.5 % Sensor Signal Conditioning Performance IC Accuracy Error 1) ErrA,IC Accuracy error for ideally linear (in temperature and measurand) sensor 0.01 %FSO Conversion Rate, 16-Bit SSC fS, SSC Conversion per second for fully corrected 16-bit measurement 3.7 245 Hz Input Input Voltage Range VINP, VINN Input voltage range at INP and INN 0.65 1.05 V Bridge Resistance RBR Full power supply disturbance rejection (PSRR) capabilities 1 10 50 k Ω Reduced PSRR, but full functionality 100 999 Ω Power-Up Start-up Time tSTA1 VDD ramp up to interface communication (see section 3.1) 1.3 ms tSTA2 VDD ramp up to analog operation 3.3 ms Wake-up Time tWUP1 Sleep to Active State interface communication 0.7 ms tWUP2 Sleep to Active State analog operation 2.7 ms |
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