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ZSSC3123AA2 Datasheet(PDF) 9 Page - Integrated Device Technology

Part # ZSSC3123AA2
Description  Capacitive Sensor Signal Conditioner
Download  63 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ZSSC3123AA2 Datasheet(HTML) 9 Page - Integrated Device Technology

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ZSSC3123 Datasheet
© 2016 Integrated Device Technology, Inc.
9
January 26, 2016
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Voltage Dependency *
PSRTEMP
VSUPPLY > VREG+0.25V
0.03
0.1
°C/V
2.3V ≤ V
SUPPLY
≤ V
REG + 0.25V
1.25
2.25
PDM Output
Output Range *
VPDM_Range
10
90
%VSUPPLY
PDM Frequency
fPDM
fSYS/8
kHz
Filter Settling Time *
, 5
tSETT
0% to 90% LPFilter 10k
Ω/400nF
9.2
ms
Ripple *
, 5
VRIPP
0% to 90% LPFilter 10k
Ω/400nF
1.0
mV/V
PDM Additional Error (Including
Ratiometricity Error)
*
EPDM
-40 to 125
°C
0.1
0.5
%
DIGITAL I/O
Voltage Output Level Low
VOL
0
0.2
VSUPPLY
Voltage Output Level High
VOH
0.8
1
VSUPPLY
Voltage Input Level Low
VIL
0
0.2
VSUPPLY
Voltage Input Level High
VIH
0.8
1
VSUPPLY
Communication Pin Input Capacitance
*
CIN
10
pF
TOTAL SYSTEM
Capacitive Tolerance Between Parts *
Ctol
All capacitive values in the
specification are subject to this
variation
±10
%
Trimmed System Frequency
fSYS
All timing in this specification is
subject to this variation.
1.76
1.85
1.94
MHz
Frequency Variation Over Voltage and
Temperature
fvar
All timing in this specification is
subject to this variation.
±10
%
Start-Up-Time *
, 6, 7
Power-on (POR) to data ready
tSTA
Fastest and slowest settings
4.25
173
ms
Update Rate (Update Mode) *
, 6, 7
tRESP_UP
Fastest and slowest settings
0.70
288
ms
Response Time (Sleep Mode) *
, 6, 7
tRESP_SL
Fastest and slowest settings
1.25
163
ms
Parasitic to Gnd Tolerance
Including package parasitics
(Pins C0, CC, and C1) *
Mult 1
10
pF
Mult 2
20
Mult 4
40
Mult 8
80
Peak-to-Peak Noise @ output
(100 measurements in 14 bit) *
NOUT
Mult 1, 2, 4, 8
5
20
LSB


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