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WM8737 Datasheet(PDF) 11 Page - Wolfson Microelectronics plc |
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WM8737 Datasheet(HTML) 11 Page - Wolfson Microelectronics plc |
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11 / 38 page  Preliminary Technical Data WM8737L w AI Rev 3.0 May 2004 11 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK t MCLKL t MCLKH t MCLKY Figure 1 System Clock Timing Requirements Test Conditions DBVDD = 3.3V, DCVDD = 1.42 to 3.6V, DGND = 0V, TA = +25 oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT System Clock Timing Information MCLK System clock pulse width high TMCLKL 13 ns MCLK System clock pulse width low TMCLKH 13 ns MCLK System clock cycle time TMCLKY 26 ns AUDIO INTERFACE TIMING – MASTER MODE BCLK (Output) ADCDAT ADCLRC (Output) t DL t DDA Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface) Test Conditions DBVDD = 3.3V, DCVDD = 1.42 to 3.6V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information ADCLRC propagation delay from BCLK falling edge tDL 0 10 ns ADCDAT propagation delay from BCLK falling edge tDDA 0 10 ns AUDIO INTERFACE TIMING – SLAVE MODE BCLK ADCLRC t BCH t BCL t BCY ADCDAT t LRSU t LRH t DD Figure 3 Digital Audio Data Timing – Slave Mode |
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