ZSC31010 Datasheet

© 2016 Integrated Device Technology, Inc.

9

January 20, 2016

1.4.

Analog Inputs versus Output Resolution

The ZSC31010 incorporates an extended 14-bit charge-balanced ADC, which allows for a single gain setting on

the pre-amplifier to handle bridge sensitivities from 1.2 to 36 mV/V while maintaining 8 to 12 bits of output reso-

lution with a default analog gain of 24. Selectable gain settings allow accommodating bridges with different

sensitivities. The tables below illustrate the minimum resolution achievable for a variety of bridge sensitivities. The

yellow shadowed fields indicate that for these input spans with the selected analog gain setting, the quantization

noise is higher than 0.1% FSO.

Table 1.1

ADC Resolution Characteristics for an Analog Gain of 6

Analog Gain 6

Input Span [mV/V]

Allowed Offset

(+/- % of Span)

1)

Minimum Guaranteed

Resolution [Bits]

Min

Typ

Max

57.3

80.0

105.8

38%

13.3

50.6

70.0

92.6

53%

13.1

43.4

60.0

79.4

73%

12.9

36.1

50.0

66.1

101%

12.6

28.9

40.0

52.9

142%

12.3

21.7

30.0

39.7

212%

11.9

Table 1.2

ADC Resolution Characteristics for an Analog Gain of 12

Analog Gain 12

Input Span [mV/V]

Allowed Offset

(+/- % of Span)

1)

Minimum Guaranteed

Resolution [Bits]

Min

Typ

Max

43.3

60.0

79.3

3%

13.0

36.1

50.0

66.1

17%

12.7

25.3

35.0

46.3

53%

12.2

18.0

25.0

33.0

101%

11.7

14.5

20.0

26.45

142%

11.4

7.2

10.0

13.22

351%

10.4

3.6

5.0

6.6

767%

9.4

Note: Yellow shadowing indicates that for these input spans with the selected analog gain setting, the quantization noise is > 0.1% FSO.