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ZSSC1750EA3R Datasheet(PDF) 5 Page - Integrated Device Technology |
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ZSSC1750EA3R Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 116 page  ZSSC1750 / ZSSC1751 Datasheet © 2016 Integrated Device Technology, Inc. 5 April 20, 2016 Figure 3.7 LP/ULP State Performing Current, Voltage, and Temperature Measurements with discCvtCnt == 2..................................................................................................................... 56 Figure 3.8 LP/ULP State Performing Current, Voltage, and Temperature Measurements with discCvtCnt == 5..................................................................................................................... 56 Figure 3.9 LP/ULP State Performing Current, Voltage, and Temperature Measurements with discCvtCnt == 1..................................................................................................................... 57 Figure 3.10 LP/ULP State Performing Continuous Current-Only Measurements ............................................... 58 Figure 3.11 Performing Continuous Current and Voltage Measurements during LP/ULP State......................... 60 Figure 3.12 Functional Block Diagram of the Analog Measurement Subsystem ................................................ 64 Figure 3.13 FP ADC Clocking Scheme for sdmPos = sdmPos2 = 2; sdmClkDivFp = 1; sdmChopClkDiv = 0........................................................................................................................ 66 Figure 3.14 FP ADC Clocking for sdmPos = 1 and sdmPos2 = 4; sdmClkDivFp = 1; sdmChopClkDiv = 0... 66 Figure 3.15 FP ADC Clocking for sdmPos = 3 and sdmPos2 = 0; sdmClkDivFp = 1; sdmChopClkDiv = 0... 67 Figure 3.16 FP ADC Clocking for sdmPos = 0 and sdmPos2 = 3; sdmClkDivFp = 1; sdmChopClkDiv = 0... 67 Figure 3.17 LP/ULP ADC Clocking Scheme; sdmClkDivLp = 5; sdmChopClkDiv = 0 ................................... 68 Figure 3.18 Functional Block Diagram of the Digital ADC Data Path .................................................................. 69 Figure 3.19 Data Post Correction ........................................................................................................................ 70 Figure 3.20 Data Representation through Data Post Correction including Over-Range and Overflow Levels ... 71 Figure 3.21 Common Enable for the “set overrange” and “set overflow” Interrupt Strobes for Current .............. 72 Figure 3.22 Individual SRCS................................................................................................................................ 87 Figure 3.23 Individual MRCS (Example for Result Counter of 3) ........................................................................ 87 Figure 3.24 Continuous SRCS............................................................................................................................. 88 Figure 3.25 Continuous MRCS (Example for Result Counter of 3) ..................................................................... 88 Figure 3.26 Stopping Continuous SRCS ............................................................................................................. 89 Figure 3.27 Stopping Continuous MRCS (Example for Result Counter of 3)...................................................... 89 Figure 3.28 Interrupting a Continuous SRCS ...................................................................................................... 90 Figure 3.29 Interrupting a Continuous MRCS (Example for Result Counter of 3)............................................... 90 Figure 3.30 Signal Behavior of adcMode ............................................................................................................ 91 Figure 3.31 Timing for Current, Voltage, and Internal Temperature Measurements without Chopping for Different Configurations of the Average Filter .................................................................................. 93 Figure 3.32 Timing for External Temperature Measurements without Chopping when No Average Filter is Enabled ............................................................................................................ 94 Figure 3.33 Timing for Current, Voltage, and Internal Temperature Measurements using Chopping................. 95 Figure 3.34 Timing for External Temperature Measurements using Chopping................................................... 96 Figure 3.35 Usage of Register adcCaccTh for the Digital ADC BIST ................................................................ 98 Figure 3.36 Bit Stream of ADC Interface Test at STO Pad ................................................................................. 99 Figure 3.37 Protection Logic of the LIN TXD Line ............................................................................................. 100 Figure 3.38 Waveform Showing the Gating Principle for Non-zero Values of linShortDelay...................... 101 Figure 4.1 Optional External Components for ZSSC1750............................................................................... 111 Figure 4.2 Optional External Components for ZSSC1751............................................................................... 111 Figure 5.1 ZSSC1750/51 PQFN36 6x6mm Package Pin-out (Top View) ....................................................... 112 Figure 5.2 Package Drawing of the ZSSC1750/51 .......................................................................................... 114 |
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