Bulletin #1512071

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W7206F2 Silicon Labs Bulletin rev N

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Use VDD Monitor high setting only when writing Flash

– Updated step 4 in section 15.4.1 VDD Maintenance and the VDD monitor on page 143 to mention using

the VDD monitor in the high setting during flash write/erase operations. To ensure the highest system

reliability, firmware can change the VDD Monitor high threshold, and the system must use an external

supply monitor.

This step previously mentioned using the VDD monitor, but did not specify that the VDD monitor must be

in the high setting in order to write to flash.

Note: The output of the internal voltage regulator is calibrated by the MCU immediately after any reset

event. The output of the un-calibrated internal regulator could be below the high threshold setting of the

VDD Monitor. If this is the case, and the MCU receives a non-power on reset (POR) when the VDD Monitor

is set to the high threshold setting, the MCU will remain in reset until a POR occurs (i.e., VDD Monitor will

keep the device in reset). A POR will force the VDD Monitor to the low threshold setting, which is

guaranteed to be below the un-calibrated output of the internal regulator. The device will then exit reset

and resume normal operation. It is for this reason Silicon Labs strongly recommends that the VDD Monitor

is always left in the low threshold setting (i.e. default value upon POR). When programming the Flash in-

system, the VDD Monitor must be set to the high threshold setting. To prevent this issue from happening

and ensure the highest system reliability, firmware can change the VDD Monitor high threshold, and the

system must use an external supply monitor. For instructions on how to do this, see “Reprogramming the

VDD Monitor High Threshold” on page 138.

Set ZTCEN before entering oscillator suspend

– Updated the SUSPEND bit description in SFR Definition 19.2 OSCICN register on page 179 to mention that

firmware must set the ZTCEN bit in SFR Definition 8.1 REF0CN on page 76 before entering suspend.

This information was already present as a note in data sheet section 16.3 Suspend Mode on page 150, and

has been added to the bit description to make it more prominent.

Internal Oscillator Suspend Enable Bit

Before entering suspend mode, firmware must set the ZTCEN bit in REF0CN

IFRDY flag does not accurately reflect the state of the oscillator

– Added a note to the IFRDY flag in the SFR Definition 19.2 OSCICN register on page 179 that the flag may

not accurately reflect the state of the oscillator.

IFRDY Internal Oscillator Frequency Ready Flag.

Note: This flag may not accurately reflect the state of the oscillator. Firmware should not use this

flag to determine if the oscillator is running.

VDD ramp time max 1 ms for power on specification

– Added VDD Ramp Time max 1 ms for Power On spec to Table 5.4 Reset Electrical Characteristics on page

48.

page 143. It is now added to the electrical specifications to make it more prominent.