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C8051F553-IM Datasheet(PDF) 4 Page - Silicon Laboratories |
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C8051F553-IM Datasheet(HTML) 4 Page - Silicon Laboratories |
4 / 5 page Bulletin #1409081 _____________________________________________________________________________________________________ W7206F2 Silicon Labs Bulletin rev I The information contained in this document is PROPRIETARY to Silicon Laboratories, Inc. and shall not be reproduced or used in part or whole without Silicon Laboratories’ written consent. The document is uncontrolled if printed or electronically saved. Pg 6 – Added a note regarding fast changes on VDD causing the VDD Monitor to trigger to “Power-Fail Reset/VDD Monitor” on page 140. Note: The VDD Monitor may trigger on fast changes in voltage on the VDD pin, regardless of whether the voltage increased or decreased. UART TX THRE0 bit may return incorrect status – Added notes regarding UART TX and RX behavior in “Data Transmission” on page 239, “Data Reception” on page 239, and the THRE0 description in the SCON0 register (SFR Definition 23.1). Note: THRE0 can have a momentary glitch high when the UART Transmit Holding Register is not empty. The glitch will occur sometime after SBUF0 was written with the previous byte and does not occur if THRE0 is checked in the instruction(s) immediately following the write to SBUF0. When firmware writes SBUF0 and SBUF0 is not empty, TX0 will be stuck low until the next device reset. Firmware should use or poll on TI0 rather than THRE0 for asynchronous UART writes that may have a random delay in between transactions. UART RX may overrun on simultaneous FIFO read/write – Added notes regarding UART TX and RX behavior in “Data Transmission” on page 239, “Data Reception” on page 239, and the THRE0 description in the SCON0 register (SFR Definition 23.1). Note: The UART Receive FIFO pointer can be corrupted if the UART receives a byte and firmware reads a byte from the FIFO at the same time. When this occurs, firmware will lose the received byte and the FIFO receive overrun flag (OVR0) will also be set to 1. Systems using the UART Receive FIFO should ensure that the FIFO isn’t accessed by hardware and firmware at the same time. In other words, firmware should ensure to read the FIFO before the next byte is received. Reason: Clarification of device behavior and inclusion of data sheet version 1.1 errata. Product Identification: C8051F550-IM C8051F551-IM C8051F552-IM C8051F553-IM C8051F554-IM C8051F555-IM C8051F556-IM C8051F557-IM C8051F560-IM C8051F560-IQ C8051F561-IM C8051F561-IQ C8051F562-IM C8051F562-IQ C8051F563-IM C8051F563-IQ C8051F564-IM C8051F564-IQ C8051F565-IM C8051F550-IMR C8051F551-IMR C8051F552-IMR C8051F553-IMR C8051F554-IMR C8051F555-IMR C8051F556-IMR C8051F557-IMR C8051F560-IMR C8051F560-IQR C8051F561-IMR C8051F561-IQR C8051F562-IMR C8051F562-IQR C8051F563-IMR C8051F563-IQR C8051F564-IMR C8051F564-IQR C8051F565-IMR |
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