U4080B

TELEFUNKEN Semiconductors

Rev. A1, 20-May-96

Preliminary Information

8 (15)

Log Amplifiers (Transmit and Receive Level Detectors)

The log amplifiers monitor the levels of the transmit and

receive signals so as to tell the I-R comparator which

mode is in operation. The input signals are applied to the

amplifiers (at TLI and RLI) through coupling capacitors

and current limiting resistors.

The value of these components determines the sensitivity

of the respective amplifiers and has an effect on the

switching times between transmit and receive modes.

The feedback elements for the amplifiers are back-to-

back diodes which provide a logarithmic gain curve, thus

allowing the operation over a wide range of signal levels.

The output of the amplifiers are rectified, having a fast

rise time and a slow decay time. The rise time (

x 1 ms)

is determined by the capacitor at Pin 6 (or Pin 8) and an

internal 500

Ω resistor.

The decay time (

x 1 s) is determined by the external RC

values at Pin 7. The switching time is not fixed, but

depends on the relative values of the transmit and receive

signals, as well as these external components. Figure 7

indicates the dc transfer characteristics of the log amps,

and figure 8 indicates the transfer characteristics with

respect to an ac input signal. The dc level at Pins 5 to 8

0

20

406080

0

50

100

150

200

250

100

94 7873 e

Figure 7.

020

40

60

0

50

100

150

80

R = 2.7 k

W

C = 0.1

mF

R = 4.7 k

W

C = 68 nF

Input

C

R

Output

Log

2.2

mF

2.2

MW

94 7874 e

Figure 8.

The T-R comparators responds to the voltages at TLO and

RLO, which in turn are functions of the currents sourced

out of TLI and RLI, respectively. If an offset at the

comparator input is desired (e.g., to prevent noise from

switching the system or to give preference to either the

transmit or receive channel) it may be achieved by biasing

the appropriate input (Pin 5 or 7). A resistor to ground will

cause a dc current to flow out of that input, thus forcing

the output of that amplifier to be biased slightly higher

than normal. This amplifier then becomes the preferred

one in the system operation. Resistor values from 500 k

Ω

to 10 M

Ω are recommended for this purpose.

Speaker Amplifier

The speaker amplifier has fixed gain of 34 dB and is non-

inverting. The input impedance is nominally 22 k

Ω as

long as the output signal is lower than required to activate

the peak limiter. Figure 9 shows the typical speaker am-

plifier output (SAO) swing at Pin 15. Since the output

current capability is 100 mA, the lower curve is limited

to a 5.0 V swing. The output impedance depends on the

output signal level and is relatively low when the signal

put impedance is

output

is

short-circuit

protected

at

approximately

300 mA.

When the amplifier is overdriven, the peak limiter causes

a portion of the input signal to be shunted to ground in or-

der to maintain a constant output level. The effect is that

of a gain reduction caused by a reduction of the input

impedance at Pin 19 (SAI) to a value not less than 2 k

Ω.

The capacitor at Pin 17 (AGC) determines the response

time of the peak limiter circuit. When a large input signal

is applied to SAI, the voltage at Pin 17 will drop quickly

as a current source is applied to the external capacitor.