F1977

7-Bit, 75 Ω

Ω

Ω

Ω, Digital Step Attenuator

6

Rev 1, 04/21/2016

16-bit shift register made up of two words. The first 8-bit word is the Attenuation word, which controls the

DSA state. The second word is the address word, which uses only 3 of 8-bits that must match the hard wired

A0-A2 programming in order to change the DSA state. If no external connections are made to A0 – A2 then

internally they will default to 000 due to internal pull down resistors. If these 3 external preset address bits

are not matched with the SPI loaded address bits then the current attenuator state will remain unchanged.

This allows up to 8 serial-controlled devices to be used on a single board, which share a common DATA, CLK

and LE.

When serial programming is used, all the parallel control input pins 26 – 32 can be left open or grounded. If a

pin is grounded than an additional 25 A will be drawn from the voltage supply per pin.

Set to either Logic High or Low

Set to Logic Low

MSB (Last In)

LSB (First In)

Q15

Q14

Q13

Q12

Q11

Q10

Q9

Q8

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

8-Bit Address Word

8-Bit Attenuation Word

Figure 2 - Two 8-bit words are comprised of 16-bit serial in, parallel out shift register

Table 1 - Truth Table for the Serial Address Word

A7

(MSB)

A6

A5

A4

A3

A2

A1

A0

Address

Setting

X

X

X

X

X

0

0

0

000

X

X

X

X

X

0

0

1

001

X

X

X

X

X

0

1

0

010

X

X

X

X

X

0

1

1

011

X

X

X

X

X

1

0

0

100

X

X

X

X

X

1

0

1

101

X

X

X

X

X

1

1

0

110

X

X

X

X

X

1

1

1

111