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ACT8865QI305-T Datasheet(PDF) 10 Page - Active-Semi, Inc |
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ACT8865QI305-T Datasheet(HTML) 10 Page - Active-Semi, Inc |
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10 / 31 page  ACT8865 Rev 7, 22-Mar-16 www.active-semi.com ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of NXP. Copyright © 2016 Active-Semi, Inc. REGISTER AND BIT DESCRIPTIONS Table 1: Global Register Map OUTPUT ADDRESS BIT NAME ACCESS DESCRIPTION SYS 0x00 [7] TRST R/W Reset Timer Setting. Defines the reset timeout threshold. See nRSTO Output section for more information. SYS 0x00 [6] nSYSMODE R/W SYSLEV Mode Select. Defines the response to the SYSLEV voltage detector, 1: Generate an interrupt when VVDDREF falls below the programmed SYSLEV threshold, 0: automatic shutdown when VVDDREF falls below the programmed SYSLEV threshold. SYS 0x00 [5] nSYSLEVMSK R/W System Voltage Level Interrupt Mask. Disabled interrupt by default, set to 1 to enable this interrupt. See the Programmable System Voltage Monitor section for more information SYS 0x00 [4] nSYSSTAT R System Voltage Status. Value is 1 when VVDDREF is lower than the SYSLEV voltage threshold, value is 0 when VVDDREF is higher than the system voltage detection threshold. SYS 0x00 [3:0] SYSLEV R/W System Voltage Detect Threshold. Defines the SYSLEV voltage threshold. See the Programmable System Voltage Monitor section for more information. SYS 0x01 [7:6] - R Reserved. SYS 0x01 [5] MSTROFF R/W Master Off Control. Set bit to 1 to turn off all regulators. The bit will be automatically cleared to 0 when nPBIN is asserted. SYS 0x01 [4] - R Reserved. SYS 0x01 [3:1] SCRATCH R/W Scratchpad Bits. Non-functional bits, maybe be used by user to store system status information. Volatile bits, which are cleared upon system shutdown. SYS 0x01 [0] SCRATCH R/W Scratchpad Bits. Non-functional bits, maybe be used by user to store system status information. Volatile bits, which are cleared upon system shutdown. REG1 0x20 [7:6] - R Reserved. REG1 0x20 [5:0] VSET1 R/W Primary Output Voltage Selection. Valid when VSEL is driven low. See the Output Voltage Programming section for more information. REG1 0x21 [7:6] - R Reserved. REG1 0x21 [5:0] VSET2 R/W Secondary Output Voltage Selection. Valid when VSEL is driven high. See the Output Voltage Programming section for more information. REG1 0x22 [7] ON R/W Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. REG1 0x22 [6] PHASE R/W Regulator Phase Control. Set bit to 1 for regulator to operate 180° out of phase with the oscillator, clear bit to 0 for regulator to operate in phase with the oscillator. REG1 0x22 [5] MODE R/W Regulator Mode Select. Set bit to 1 for fixed-frequency PWM under all load conditions, clear bit to 0 to transit to power-savings mode under light-load conditions. REG1 0x22 [4:2] DELAY R/W Regulator Turn-On Delay Control. See the REG1, REG2, REG3 Turn-on Delay section for more information. REG1 0x22 [1] nFLTMSK R/W Regulator Fault Mask Control. Set bit to 1 enable to fault- interrupts, clear bit to 0 to disable fault-interrupts. |
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