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ACT4524YH-T Datasheet(PDF) 2 Page - Active-Semi, Inc |
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ACT4524YH-T Datasheet(HTML) 2 Page - Active-Semi, Inc |
2 / 16 page ACT4524 Rev 1.1, 22-Feb-16 Innovative PowerTM - 2 - www.active-semi.com Copyright © 2015 Active-Semi, Inc. ORDERING INFORMATION PIN CONFIGURATION PIN DESCRIPTIONS PIN NAME DESCRIPTION 1 CSP Voltage Feedback Input. The voltage at this pin is regulated to 5.10V. Connect this pin to the positive terminal of current sense resistor. CSP, CSN1 and CSN2 Kevin sense is recommended. 2 CSN1 Output current sense. Connect to the negative terminal of current sense resistor for VOUT1. 3 CSN2 Output current sense. Connect to the negative terminal of current sense resistor for VOUT2. 4 MODE Mode pin with internal pull up current to determine device should operate in Native, Master, or Slave mode. If the pin is floated, the device operates in native mode; if the pin is grounded ,the device operates in Slave mode and receives CLK signal from another device; if the pin is connected to 82kOhm resistor, the device is configured in Master mode. 5 CLK Synchronization of dual chips. Two chips operate synchronously out of phase with CLK pin connected. 6 IN Power Supply Input. Bypass this pin with a 10μF ceramic capacitor to GND, placed as close to the IC as possible. 7 SW Power switching output to external inductor. 8 HSB High Side Bias pin. This pin provides power to the internal high-side MOSFET gate driver. Connect a 22nF capacitor from HSB pin to SW pin. 9 GND Ground and heat dissipation pad. Connect this exposed pad to large ground copper area and other ground planes by thermal vias. 8 7 6 5 1 2 3 4 CSP CSN1 GND MODE IN CLK SW HSB EP ACT4524 SOP-8EP CSN2 Top View PART NUMBER OPERATION AMBIENT TEMPERATURE RANGE PACKAGE PINS PACKING ACT4524YH-T -40°C to 85°C SOP-8EP 8 TAPE & REEL |
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