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SN74LVC2G00DCUTE4 Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LVC2G00DCUTE4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 13 page www.ti.com FEATURES DCT OR DCU PACKAGE (TOP VIEW) 1 2 3 4 8 7 6 5 1A 1B 2Y GND VCC 1Y 2B 2A 4 3 2 1 5 6 7 8 GND 2Y 1B 1A 2A 2B 1Y VCC YEA, YEP, YZA OR YZP PACKAGE (BOTTOM VIEW) DESCRIPTION/ORDERING INFORMATION SN74LVC2G00 DUAL 2-INPUT POSITIVE-NAND GATE SCES193J – APRIL 1999 – REVISED JULY 2005 • Available in the Texas Instruments NanoStar™ and NanoFree™ Packages • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10- µA Max I CC • ±24-mA Output Drive at 3.3 V • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C • Ioff Supports Partial-Power-Down Mode Operation • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) This dual 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G00 performs the Boolean function Y = A ⋅ B or Y = A + B in positive logic. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING(2) NanoStar™ – WCSP (DSBGA) SN74LVC2G00YEAR 0.17-mm Small Bump – YEA NanoFree™ – WCSP (DSBGA) SN74LVC2G00YZAR 0.17-mm Small Bump – YZA (Pb-free) Reel of 3000 _ _ _CA_ NanoStar™ – WCSP (DSBGA) SN74LVC2G00YEPR 0.23-mm Large Bump – YEP –40°C to 85°C NanoFree™ – WCSP (DSBGA) SN74LVC2G00YZPR 0.23-mm Large Bump – YZP (Pb-free) SSOP – DCT Reel of 3000 SN74LVC2G00DCTR C00_ _ _ Reel of 3000 SN74LVC2G00DCUR VSSOP – DCU C00_ Reel of 250 SN74LVC2G00DCUT (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YEA/YZA,YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar, NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 1999–2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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