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BCM43364KUBGT Datasheet(PDF) 6 Page - Cypress Semiconductor |
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BCM43364KUBGT Datasheet(HTML) 6 Page - Cypress Semiconductor |
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6 / 68 page  Document Number: 002-14781 Rev. *C Page 6 of 68 PRELIMINARY CYW43364 2. Power Supplies and Power Management 2.1 Power Supply Topology One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43364. All regulators are programmable via the PMU to simplify the power supply. A single VBAT (3.0V to 4.8V DC maximum) and VDDIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by the regulators in the CYW43364. The WL_REG_ON control signal is used to power up the regulators and take the respective circuit blocks out of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only when WL_REG_ON is deasserted. The CLDO and LNLDO can be turned on and off based on the dynamic demands of the digital baseband. The CYW43364 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO regulators. When in this state, LPLDO1 provides the CYW43364 with all required voltage, further reducing leakage currents. Notes: VBAT should be connected to the LDO_VDDBAT5V and SR_VDDBAT5V pins of the device. VDDIO should be connected to the SYS_VDDIO and WCC_VDDIO pins of the device. 2.2 CYW43364 PMU Features The PMU supports the following: ■ VBAT to 1.35Vout (170 mA nominal, 370 mA maximum) Core-Buck (CBUCK) switching regulator ■ VBAT to 3.3Vout (250 mA nominal, 450 mA maximum 800 mA peak maximum) LDO3P3 ■ 1.35V to 1.2Vout (100 mA nominal, 150 mA maximum) LNLDO ■ 1.35V to 1.2Vout (80 mA nominal, 200 mA maximum) CLDO with bypass mode for deep sleep ■ Additional internal LDOs (not externally accessible) ■ PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from extremely low power-consumption mode. Figure 3 on page 7 and Figure 4 on page 8 show the typical power topology of the CYW43364. |
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