MB91F577CHSPMC datasheet(2/163 Pages) CYPRESS

Part #	MB91F577CHSPMC

Description	32-bit RISC, load/store architecture, 5-stage pipeline

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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2 / 163 page

Document Number: 002-04725 Rev.*A

Page 2 of 163

MB91570 Series

A/D converter (successive approximation type)



8/10-bit resolution : 40 channels



Conversion time : 3μs

D/A converter (R-2R type)



8-bit resolution : 2 channels

External interrupt input: 16 channels



Level ("H" / "L"), or edge detection ( rising or falling )

enabled

LIN-UART



6 channels, ch.2 to ch.7



Selectable from UART, synchronous mode or LIN-UART

mode



LIN protocol Revision 2.1 supported (LIN-UART).



SPI( Serial Peripheral Interface ) supported ( synchronous

mode )



Full-duplex double buffering system



LIN synch break detection ( linked to the input capture )



Built-in dedicated baud rate generator



DMA transfer support

Multi-function serial communication (built-in

transmission/reception FIFO memory ) : 4 channels

< UART (Asynchronous serial interface) >



Full-duplex double buffering system, 16-byte transmission

FIFO memory, 16-byte reception FIFO memory



Parity or no parity is selectable.



Built-in dedicated baud rate generator



The external clock can be used as the transfer clock



Parity, frame, and overrun error detect functions provided



DMA transfer support



Full-duplex double buffering system, 16-byte transmission

FIFO, memory, 16-byte reception FIFO memory



SPI supported; master and slave systems supported; 5 to

9-bit data length can be set.



Built-in dedicated baud rate generator (Master operation)



The external clock can be entered. (Slave operation)



Overrun error detection function is provided



DMA transfer support

<LIN-UART (Asynchronous Serial Interface for

LIN) >



Full-duplex double buffering system, 16-byte transmission

FIFO memory, 16-byte reception FIFO memory



LIN protocol revision 2.1 supported



Master and slave systems supported



Framing error and overrun error detection



LIN synch break generation and detection; LIN synch

delimiter generation



Built-in dedicated baud rate generator



The external clock can be adjusted by the reload counter



DMA transfer support

< I

2C >



Full-duplex double buffering system, 16-byte transmission

FIFO memory, 16-byte reception FIFO memory



Standard mode ( Max. 100kbps ) / high-speed mode ( Max.

400kbps ) supported



DMA transfer supported ( for transmission only )



I

2C supporting I/O ( for ch.0 and ch.1 only )

CAN Controller (C-CAN) : 3 channels



Transfer speed : Up to 1Mbps



64-transmission/reception message buffering : 1 channel,

32-transmission/reception message buffering : 2 channels

PPG : 16-bit × 24 channels

Reload timer : 16-bit × 7 channels(3 channels are for regular

timer interrupt generation. )

Free-run timer :

32-bit × 6 channels (Can select each channel for input

capture, output compare)

Input capture :

32-bit × 12 channels (linked to the free-run timer)

Output compare : 32-bit × 12 channels (linked to the free-run

timer)

Sound generator : 5 channels



Frequency and amplitude sequencers provided

Stepping motor controller : 6 channels



8/10-bit PWM



High current output supported (4 lines × 6 channels)



Can refer back electromotive force using pin-shared A/D

converter

LCD controller



Common output : 4 , Segment output : 32



Duty drive (SEG0 to SEG31) and static drive (ST0 to ST8)

can be switched.



Each of COM0 to COM3, SEG0 to SEG31, V0, V1, V2, and

V3 pins for duty drive can be switched to the

general-purpose port. (The SEG23 to SEG31 pins can be

switched to static driving.)



V0, V1, V2 and V3 pin can be used as the general-purpose

port. But V3 pin cannot be used as an output pin.



Each of ST0 to ST8 pins for static drive can be switched to

the general-purpose port, or it can be switched to the

segment output of duty drive.



MB91F575/7: The amplitude of the SEG0 to SEG22 output

is determined by the VCC5 power supply pin or by the V3

pin even if VCCE pin is supplied to 3.3V.



MB91F578/9: The voltage VCCE or less can be supplied to

V3 pin. It is prohibited that VCC5 being chosen as LCDC

reference voltage by software.

Up/Down counter: 2 channels



8/16-bit up/down counter

Real-time clock (RTC) (for day, hours, minutes, seconds)



Main oscillation / sub oscillation frequency can be selected

for the operation clock

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