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MPC750 RISC Microprocessor Technical Summary

1.1 MPC750 Microprocessor Features

This section lists features of the MPC750. The interrelationship of these features is shown in Figure 1.

1.1.1 Overview of the MPC750 Microprocessor Features

Major features of the MPC750 are as follows:

•

High-performance, superscalar microprocessor

— As many as four instructions can be fetched from the instruction cache per clock cycle

— As many as two instructions can be dispatched per clock

— As many as six instructions can execute per clock (including two integer instructions)

— Single-clock-cycle execution for most instructions

•

Six independent execution units and two register files

— BPU featuring both static and dynamic branch prediction

– 64-entry (16-set, four-way set-associative) branch target instruction cache (BTIC), a cache

of branch instructions that have been encountered in branch/loop code sequences. If a target

instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can

be made available from the instruction cache. Typically, if a fetch access hits the BTIC, it

provides the first two instructions in the target stream.

– 512-entry branch history table (BHT) with two bits per entry for four levels of prediction—

not-taken, strongly not-taken, taken, strongly taken

– Branch instructions that do not update the count register (CTR) or link register (LR) are

removed from the instruction stream.

— Two integer units (IUs) that share thirty-two GPRs for integer operands

– IU1 can execute any integer instruction.

– IU2 can execute all integer instructions except multiply and divide instructions (multiply,

divide, shift, rotate, arithmetic, and logical instructions). Most instructions that execute in

the IU2 take one cycle to execute. The IU2 has a single-entry reservation station.

— Three-stage FPU

– Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations

– Supports non-IEEE mode for time-critical operations

– Hardware support for denormalized numbers

– Single-entry reservation station

– Thirty-two 64-bit FPRs for single- or double-precision operands

— Two-stage LSU

– Two-entry reservation station

– Single-cycle, pipelined cache access

– Dedicated adder performs EA calculations

– Performs alignment and precision conversion for floating-point data

– Performs alignment and sign extension for integer data

– Three-entry store queue

– Supports both big- and little-endian modes

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