HMC7044 datasheet(4/72 Pages) AD

Part #	HMC7044

Description	JESD204B clock generation

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HMC7044

Data Sheet

Rev. B | Page 4 of 72

DIGITAL INPUT/OUTPUT (I/O) ELECTRICAL SPECIFICATIONS

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIGITAL INPUT SIGNALS (RESET, SYNC, SLEN, SCLK)

Safe Input Voltage Range1

−0.1

+3.6

V

Input Load

0.3

pF

Input Voltage

Input Logic High (VIH)

1.2

VCC

V

Input Logic Low (VIL)

0

0.5

V

SPI Bus Frequency

10

MHz

DIGITAL BIDIRECTIONAL SIGNALS CONFIGURED AS

INPUTS (SDATA, GPIO4, GPIO3, GPIO2, GPIO1)

Safe Input Voltage Range1

−0.1

+3.6

V

Input Capacitance

0.4

pF

Input Resistance

50G

Ω

Input Voltage

Input Logic High (VIH)

1.22

VCC

V

Input Logic Low (VIL)

0

0.24

V

Input Hysteresis

0.2

V

Occurs around 0.85 V

GPIO1 TO GPIO4 ALARM MUXING/DELAY

Delay from Internal Alarm/Signal to General-Purpose

Output (GPO) Driver

2

ns

Does not include tDGPO

DIGITAL BIDIRECTIONAL SIGNALS CONFIGURED AS

OUTPUTS (SDATA, GPIO4, GPIO3, GPIO2, GPIO1)

CMOS MODE

Logic 1 Level

1.6

1.9

2.2

V

Logic 0 Level

0

0.1

V

Output Drive Resistance (RDRIVE)

50

Ω

Output Driver Delay (tDGPO)

1.5 + 42 ×

CLOAD

ns

Approximately 1.5 ns + 0.69 × RDRIVE × CLOAD

(CLOAD in nF)

Maximum Supported DC Current1

0.6

mA

OPEN-DRAIN MODE1

External 1 kΩ pull-up resistor

Logic 1 Level

3.6

V

3.6 V maximum permitted; specifications

set by external supply

Logic 0 Level

0.13

0.28

V

Against a 1 kΩ external pull-up resistor to

3.3 V

Pull-Down Impedance

60

Ω

Maximum Supported Sink Current

5

mA

1

Guaranteed by design and characterization.

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