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HMC7043LP7FE Datasheet(PDF) 3 Page - Analog Devices |
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HMC7043LP7FE Datasheet(HTML) 3 Page - Analog Devices |
3 / 44 page HMC7043 Data Sheet Rev. B | Page 2 of 43 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Conditions..................................................................................... 3 Supply Current.............................................................................. 3 Digital Input/Output (I/O) Electrical Specifications............... 4 Clock Input Path Specifications.................................................. 4 Additive Jitter and Phase Noise Characteristics....................... 5 Clock Output Distribution Specifications................................. 5 Clock Output Driver Characteristics......................................... 6 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 11 Typical Application Circuits.......................................................... 13 Terminology.................................................................................... 14 Theory of Operation ...................................................................... 15 Detailed Block Diagram ............................................................ 16 Clock Input Network ................................................................. 16 Clock Output Network .............................................................. 17 Typical Programming Sequence............................................... 23 Power Supply Considerations................................................... 24 Serial Control Port ......................................................................... 27 Serial Port Interface (SPI) Control........................................... 27 Control Registers............................................................................ 28 Control Register Map ................................................................ 28 Control Register Map Bit Descriptions ................................... 33 Applications Information .............................................................. 41 Evaluation PCB And Schematic............................................... 41 Outline Dimensions....................................................................... 43 Ordering Guide .......................................................................... 43 REVISION HISTORY 7/2016—Rev. A to Rev. B Changes to Table 1............................................................................ 3 5/2016—Rev. 0 to Rev. A Changes to Table 3 ............................................................................. 4 Change to Maximum Operating Frequency Parameter, Table 7..... 7 Added Figure 6, Renumbered Sequentially ................................ 11 Change to Synchronization FSM/Pulse Generator Timing Section................................................................................. 21 Changes to Table 20........................................................................ 28 Change to Table 22 ......................................................................... 33 Changes to Table 28........................................................................ 34 Changes to Table 29........................................................................ 35 Change to Table 31 ......................................................................... 36 Change to Table 38 ......................................................................... 37 Changes to Table 41........................................................................ 39 12/2015—Revision 0: Initial Version |
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