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MC68328 PRODUCT INFORMATION

MOTOROLA

External Bus Interface

The external bus interface handles the transfer of information between the internal 68EC000 core and the

memory, peripherals, or other processing elements in the external address space. It consists of a 16-bit 68000

bus interface for internal and a selectable 8-bit or 16-bit interface to outside.

Interrupt Controller

The interrupt controller accepts and prioritizes both internal and external interrupt requests and generates a

vector number during the CPU interrupt acknowledge cycle. Interrupt nesting is also provided so that an inter-

rupt service routine of a lower priority interrupt may be suspended by a higher priority interrupt request. The

on-chip interrupt controller has the following major features:

• Prioritized Interrupt Sources (Internal and External)

• A Fully Nested Interrupt Environment

• Programmable Vector Generation

• Interrupt Masking

• Wake-up interrupt Masking

Parallel General-Purpose I/O Ports

The MC68328 supports up to 78-bit general-purpose I/O ports, which can be configured as general-purpose

I/O pins or as dedicated peripheral interface pins of the on-chip modules.

Each port pin can be independently programmed as general-purpose I/O pins, even when other pins related

to the same on-chip peripheral are used as dedicated pins. Even if all the pins for a particular peripheral are

configured as general-purpose I/O, the peripheral will still operate normally, although this is only useful in the

case of the RTC and timer modules.

Software Watchdog

A software watchdog timer is used to protect against system failures by providing a means to escape from

unexpected input conditions, external events, or programming errors. Once started, the software watchdog

timer must be cleared by software on a regular basis so that it never reaches its time-out value. Upon reaching

the time-out value, the assumption is made that a system failure has occurred, and the software watchdog logic

resets or interrupts the 68EC000 core.

Low-Power Stop Logic

Various options for power-saving are available: turning off unused peripherals, reducing processor clock

speed, disabling the processor altogether or a combination of these.

A wake-up from low-power mode can be achieved by causing an interrupt at the interrupt controller logic which

runs throughout the period of processor low-power. Selectable interrupt will cause a wake-up of the EC000

core followed by processing of that interrupt.

The on-chip peripherals can initiate a wake-up; for example, the timer can be set to wake-up after a certain

elapsed time, or number of external events.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com