ICS93712YF-PPP-T datasheet(3/6 Pages) ICST

Part #	ICS93712YF-PPP-T

Description	2 DIMM DDR Fanout Buffer

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Manufacturer	ICST [Integrated Circuit Systems]

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3

ICS93712

Advance Information

Byte6:OutputControl

(1= enable, 0 = disable)

Byte7:OutputControl

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

1

)

d

e

v

r

e

s

e

R

(

6

t

i

B-

0

)

d

e

v

r

e

s

e

R

(

5

t

i

B-

0

)

d

e

v

r

e

s

e

R

(

4

t

i

B-

0

)

d

e

v

r

e

s

e

R

(

3

t

i

B-

1

*

)

d

e

v

r

e

s

e

R

(

2

t

i

B6

2

,

7

21

5

C

R

D

,

5

T

R

D

1

t

i

B2

2

,

3

21

4

C

R

D

,

4

T

R

D

0

t

i

B8

1

,

9

11

3

C

R

D

,

3

T

R

D

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

1

*

d

e

v

r

e

s

e

R

6

t

i

B-

1

*

d

e

v

r

e

s

e

R

5

t

i

B-

1

*

d

e

v

r

e

s

e

R

4

t

i

B3

1

,

2

11

2

T

R

D

2

C

R

D

3

t

i

B-

1

*

d

e

v

r

e

s

e

R

2

t

i

B8

,

71

1

T

R

D

1

C

R

D

1

t

i

B-

1

*

d

e

v

r

e

s

e

R

0

t

i

B4

,

31

0

C

R

D

,

0

T

R

D

Note:

* For lower power consumption, these bits should be driven to 0.

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

1

d

e

v

r

e

s

e

R

6

t

i

B-

1

d

e

v

r

e

s

e

R

5

t

i

B-

1

d

e

v

r

e

s

e

R

4

t

i

B-

1

d

e

v

r

e

s

e

R

3

t

i

B-

1

d

e

v

r

e

s

e

R

2

t

i

B-

1

d

e

v

r

e

s

e

R

1

t

i

B-

1

d

e

v

r

e

s

e

R

0

t

i

B-

1

d

e

v

r

e

s

e

R

Byte 5: Reserved Register

(1= enable, 0 = disable)

Notes:

1. Refers to transition on noninverting output.

2. While the pulse skew is almost constant over frequency, the duty cycle error increases at

higher frequencies. This is due to the formula: duty cycle=twH/tc, were the cycle (tc)

decreases as the frequency goes up.

Switching Characteristics

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

Maximum Operating Frequency

66

200

MHz

Input clock duty cycle

dtin

40

60

%

Output to Output Skew

Tskew

100

ps

Pulse skew

Tskewp

100

ps

66MHz to 100MHz

48

52

%

101MHz to 167MHz

47

53

%

Rise Time, Fall Time

tr, tf

Load = 120

Ω/16pF

650

950

ps

Duty cycle

DC

2

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ICS93712YF-PPP-T Datasheet(PDF) 3 Page - Integrated Circuit Systems

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