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ICS9DB108YFLFT Datasheet(PDF) 4 Page - Integrated Circuit Systems |
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ICS9DB108YFLFT Datasheet(HTML) 4 Page - Integrated Circuit Systems |
4 / 15 page 4 Integrated Circuit Systems, Inc. ICS9DB108 0723D—01/08/04 ICS9DB108 follows the Intel DB400 Differential Buffer Specification. This buffer provides four SRC clocks for PCI-Express, next generation I/O devices. ICS9DB108 is driven by a differential input pair from a CK409/CK410 main clock generator, such as the ICS952601 or ICS954101. ICS9DB108 can run at speeds up to 200MHz. It provides ouputs meeting tight cycle-to-cycle jitter (50ps) and output-to-output skew (50ps) requirements. General Description Block Diagram STOP LOGIC SRC_IN SRC_IN# DIF(7:0) CONTROL LOGIC HIGH_BW# BYPASS#/PLL SDATA SCLK SRC_STOP# PD# SPREAD COMPATIBLE PLL 8 IREF OE(7:0) 8 SRC_DIV# |
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