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ZSPM1501ZA1W0 Datasheet(PDF) 30 Page - Integrated Device Technology

Part # ZSPM1501ZA1W0
Description  True-Digital PWM Controller
Download  101 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ZSPM1501ZA1W0 Datasheet(HTML) 30 Page - Integrated Device Technology

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ZSPM15xx Datasheet
© 2016 Integrated Device Technology, Inc.
30
January 27, 2016
3.3.3.
Digital Compensator
The sampled output voltage is processed by a digital control loop in order to modulate the DPWM output signals
controlling the power stage. This digital control loop works as a voltage-mode controller using a PID-type
compensation. The basic structure of the controller is shown in Figure 3.1. The proprietary State-Law™ Control
(SLC) concept features two parallel compensators for steady-state operation and fast transient operation. This
allows tuning the compensators individually for the respective needs; i.e., quiet steady state and fast transient
performance. The ZSPM15xx implements fast, reliable switching between the different compensation modes in
order to ensure good transient performance and a quiet steady state.
Figure 3.1
Simplified Block Diagram of the Digital Compensation
Two techniques are used to improve transient performance further:
Tru-sample Technology™ is used to acquire fast, accurate, and continuous information about the output vol-
tage so that the device can react quickly to any change in output voltage. Tru-sample Technology™ reduces
phase-lag caused by sampling delays, reduces noise sensitivity, and improves transient performance.
A nonlinear gain adjustment is used during large load transients to boost the loop gain and reduce the
settling time.
The control loops in the ZSPM15xx are preconfigured and can be selected using a pin-strapping option. A range
of different output capacitors is supported. Refer to section 4.8 for detailed information.
Digital PID
Compensator
Steady-state
Transient
Coefficients
Non-linear
Gain
Operation
Mode
Detection
Digital Error Signal
Duty Cycle


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