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SA56614-45 Datasheet(PDF) 8 Page - NXP Semiconductors |
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SA56614-45 Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 14 page  Philips Semiconductors Product data SA56614-XX CMOS system reset 2001 Jun 19 8 TIMING DIAGRAM The timing diagram shown in Figure 13 depicts the operation of the device. Letters A-J on the TIME axis indicate specific events. A: At ‘A’, VDD begins to increase. Also the VOUT voltage initially increases but abruptly decreases when VDD reaches the level (approximately 0.8 V) that activates the internal bias circuitry and RESET is asserted. B: At ‘B’, VDD reaches the threshold level of VSH. At this point the device releases the hold on the VOUT reset. The Reset output VOUT tracks VDD as it rises above VSH (assuming the reset pull-up resistor RPU is connected to VDD). In a microprocessor based system these events release the reset from the microprocessor, allowing the microprocessor to function normally. C-D: At ‘C’, VDD begins to fall, causing VOUT to follow. VDD continues to fall until the VSL undervoltage detection threshold is reached at ‘D’. This causes a reset signal to be generated (VOUT Reset goes LOW). D-E: Between ‘D’ and ‘E’, VDD starts rising. E: At ‘E’, VDD rises to the VSH. Once again, the device releases the hold on the VOUT reset. The Reset output VOUT tracks VDD as it rises above VSH. F-G: At ‘F’, VDD is above the upper threshold and begins to fall, causing VOUT to follow it. As long as VDD remains above the VSH, no reset signal will be triggered. Before VDD falls to the VSH, it begins to rise, causing VOUT to follow it. At ‘G’, VDD returns to normal. H: At event ‘H’ VDD falls until the VSL undervoltage detection threshold point is reached. At this level, a RESET signal is generated and VOUT goes LOW. J: At ‘J’ the VDD voltage has decreased until normal internal circuit bias is unable to maintain a VOUT reset. As a result, VDD may rise to less than 0.8 V. As VDD decreases further, VOUT reset also decreases to zero. SL01354 VDD VOUT TIME VSH VSL 0 0 AB C G H J DE F ∆VS Figure 13. Timing diagram. |
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