PCF85116 datasheet(7/20 Pages) PHILIPS

Part #	PCF85116

Description	Low power CMOS: maximum operating current 1.0 mA

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Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

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1997 Apr 02

7

Philips Semiconductors

Product speciﬁcation

2048

× 8-bit CMOS EEPROM with I2C-bus

interface

PCF85116-3

8.3

Device addressing

Following a START condition the bus master must output

the address of the slave it is accessing. The 4 MSBs of the

slave address are the device type identifier (see Fig.3).

For the PCF85116-3 this is fixed to ‘1010’.

The next three significant bits of the slave address field are

the block selection bits. It is used by the host to select one

out of eight blocks (1 block = 256 bytes of memory). These

are, in effect, the three most significant bits of the word

address.

The last bit of the slave address defines the operation to

be performed. When R/W is set to logic 1 a read operation

is selected.

8.4

Write operations

8.4.1

BYTE/WORD WRITE

For a write operation the PCF85116-3 requires a second

address field. This address field is a word address

providing access to any one of the eight blocks of memory.

Upon receipt of the word address the PCF85116-3

responds with an acknowledge and awaits the next eight

bits of data, again responding with an acknowledge. Word

address is automatically incremented. The master

terminates the transfer by generating a STOP condition.

After this stop condition the E/W cycle starts and the bus

is free for another transmission. Its duration is maximum

10 ms.

During the E/W cycle the slave receiver does not send an

acknowledge bit if addressed via the I2C-bus.

Fig.3 Slave address.

handbook, halfpage

MBH924

101

0

B

R/W

8.4.2

PAGE WRITE

The PCF85116-3 is capable of an 32-byte page write

operation. It is initiated in the same manner as the byte

write operation. The master can transmit up to 32 data

bytes within one transmission. After receipt of each byte

the PCF85116-3 will respond with an acknowledge.

The master terminates the transfer by generating a STOP

condition. The maximum total E/W time in this mode is

10 ms.

After the receipt of each data byte the six high order bits of

the memory address providing access to one of the

64 pages of the memory remain unchanged. The five low

order bits of the memory address will be incremented only

(see Fig.3). By these five bits a single byte within the page

in access is selected. By an increment the memory

address may change from 31 to 0, from 63 to 32, etc. If the

master transmits more than 32 bytes prior to generating

the STOP condition, data within the addressed page may

be overwritten and unpredictable results may occur. As in

the byte write operation, all inputs are disabled until

completion of the internal write cycles.

8.4.3

REMARK

Write accesses to the EEPROM are enabled if the pin WP

is LOW. When WP is HIGH the EEPROM is

write-protected and no acknowledge will be given by the

PCF85116-3 when data is sent. However, an

acknowledge will be given after the slave address and the

word address.

Fig.4 Auto increment of memory address.

handbook, halfpage

MBH925

B

WORD ADDRESS

read: auto increment

write: unchanged

write: auto increment

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