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CDP1854 Datasheet(PDF) 5 Page - Intersil Corporation

Part No. CDP1854
Description  High Reliability CMOS Programmable Universal Asynchronous Receiver/Transmitter (UART)
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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5-66
NOTES:
1. The holding register is loaded on the trailing edge of TPB.
2. The transmitter shift register, if empty, is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + tTC
after the trailing edge of TPB and transmission of a start bit occurs 1/2 clock period + tCD later.
3. Write is the overlap of TPB, CS1, and CS3 = 1 and CS3, RD/WR = 0
FIGURE 1. TRANSMITTER TIMING DIAGRAM - MODE 1
T CLOCK
THRE
WRITE (TPB)
SDO
tCC
tCL
tCH
12
tTTH
tCD
tCD
1ST DATA BIT
TRANSMITTER SHIFT
REGISTER LOADED
(NOTE 2)
TRANSMITTER HOLDING
REGISTER LOADED
(NOTE 1)
34
56
7
14
15
16
1
23
4
tTT
(NOTE 3)
tCTH
NOTES:
1. If a start bit occurs at a time less than tDC before a high-to-low transition of the clock, the start bit may not be recognized until the next
high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.
2. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0. If a pending DA has not been cleared by a read of the receiver holding register
by the time a new word is loaded into the receiver holding register, the OE signal will come true.
3. OE and PE share terminal 15 and are also available as two separate bits in the status register.
FIGURE 2. MODE 1 RECEIVER TIMING DIAGRAM
R CLOCK
READ
tCC
tCL
tCH
tDC
12
START BIT
tTDA
CLOCK 7 1/2
SAMPLE
34
56
7
16
(NOTE 1)
SDI
12
34
56
78
9
STOP BIT 1
CLOCK 7 1/2 LOAD
HOLDING REGISTER
tCDA
tTT
tCOE
tCPE
tCFE
OE
PE
(NOTE 3)
FE
PARITY
DA
(NOTE 2)
TPB
(NOTE 3)
CDP1854A/3, CDP1854AC/3




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